Datasheet > VS8005FI

VS8005FI

更新时间： 2024-11-14 15:57:43

品牌	Logo	应用领域
VITESSE		驱动逻辑集成电路
页数	文件大小	规格书
14页	142K
描述
Telecom Circuit, 1-Func, CQFP28, HEAT SINK, CERAMIC, LDCC-28

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VS8005FI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	HQFF,
针数：	28	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.89
Is Samacsys：	N	JESD-30 代码：	S-CQFP-F28
JESD-609代码：	e0	长度：	11.43 mm
负电源额定电压：	-5.2 V	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	HQFF	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG	认证状态：	Not Qualified
座面最大高度：	2.438 mm	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.43 mm	Base Number Matches：	1

VS8005FI 数据手册

VS8004/8005

VITESSE

Data Sheet

2.5 Gbits/sec 4-Bit Multiplexer/

Demultiplexer Chipset

Features

• Differential or Single-Ended Inputs and Outputs

• Low Power Dissipation: 1.5 W (Typ. Per Chip)

• Standard ECL Power Supply: VEE = -5.2 V

• Serial Data Rates up to 2.5 Gb/s

• Parallel Data Rates up to 625 Mb/s

• ECL 100K Compatible Parallel Data I/Os

• Available in Commercial (0° to +70°C) or Indus-

trial (-40° to +85°C) Temperature Ranges

• Divide-by-4 Clock for Synchronization of

Parallel Data to Interfacing Chips

• Proven E/D Mode GaAs Technology

• 28-pin Leaded Ceramic Chip Carrier

• SKIP Input on Demux for Realignment of

Output Word Boundaries

Functional Description

The VS8004 and VS8005 are data conversion devices capable of serial data rates up to 2.5 Gb/s, transform-

ing 4-bit wide parallel data to serial data and serial data to 4-bit wide parallel data.

The VS8004/VS8005 are fabricated in gallium arsenide using the Vitesse H-GaAs™ E/D MESFET process

which achieves high speed and low power dissipation. These products are packaged in a ceramic 28-pin leaded

chip carrier.

VS8004

The VS8004 is a high speed 4 bit parallel to serial data converter suitable for digital voice or data communi-

cations applications. All inputs and outputs can be used differentially or single-ended. The parallel inputs

[D(0:3), ND(0:3)] accept data at rates up to 625 Mb/s. The differential serial data output (SDATA, NSDATA)

presents the data sequentially from the parallel data inputs at rates up to 2.5 Gb/s, synchronous with the differ-

ential high speed clock input (CLK, NCLK). An internal timing generator receives the high speed clock input

and divides it by four to create a differential clock output (CLK4, NCLK4). This clock signal is provided so that

incoming parallel signals can be synchronized to arrive at the input data registers simultaneously. An internal

bias network is provided at all inputs to simplify capacitive coupling.

VS8005

The VS8005 is a high speed 4-bit serial to parallel data converter suitable for digital voice or data commu-

nications applications. All inputs and outputs can be used differentially or single-ended. The differential serial

data inputs (SDATA, NSDATA) accept data at rates up to 2.5 Gb/s, synchronous with the differential high speed

clock input (CLK, NCLK). The parallel outputs [D(0:3), ND(0:3)] present the data sequentially at rates up to

625 Mb/s. An internal timing generator receives the high speed clock input and divides it by four to create a dif-

ferential clock output (CLK4, NCLK4) which is synchronous with the parallel data outputs. A control input

(SKIP, NSKIP) is provided to allow realignment of the output parallel word boundaries.

SKIP Signal

The SKIP signal is provided to allow realignment of the output parallel 4-bit word boundaries. Within the

current CLK4, the rising edge of a SKIP causes an internal circuit in the VS8005 to hold the current 4-bit word

output and drop the ﬁfth output bit. The sixth output bit will become the MSB of the next 4-bit word output; and

G52012-0 Rev. 2.0

® VITESSE Semiconductor Corporation

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