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VRC5074 PDF预览

VRC5074

更新时间： 2024-10-16 20:09:43
品牌 Logo 应用领域
日电电子 - NEC 时钟PC
页数 文件大小 规格书
224页 3558K
描述
Multifunction Peripheral, CMOS, PBGA500, 40 X 40 MM, HEAT SPREADER, TBGA-500

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中文翻译

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VRC5074 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：500
Reach Compliance Code：compliant风险等级：5.89
地址总线宽度：64边界扫描：NO
总线兼容性：PCI; 68000; VR5000最大时钟频率：66 MHz
外部数据总线宽度：64JESD-30 代码：S-PBGA-B500
JESD-609代码：e0长度：40 mm
I/O 线路数量：7端子数量：500
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：40 mmBase Number Matches：1

VRC5074 数据手册

 浏览型号VRC5074的Datasheet PDF文件第2页浏览型号VRC5074的Datasheet PDF文件第3页浏览型号VRC5074的Datasheet PDF文件第4页浏览型号VRC5074的Datasheet PDF文件第5页浏览型号VRC5074的Datasheet PDF文件第6页浏览型号VRC5074的Datasheet PDF文件第7页 
RC  
V 5074 System Controller  
June 1998  
Data Sheet  
1.0  
Introduction  
RC  
1.1  
The V 5074 System Controller is a software-configurable chip that directly connects  
R
the V 5000 CPU to SDRAM memory, a PCI Bus, and a Local Bus, without external  
Overview  
logic or buffering. From the CPU’s viewpoint, the controller acts as a memory control-  
ler, DMA controller, PCI-Bus host bridge, and Local-Bus host bridge. From the view-  
point of PCI agents, the controller acts as master and target on the PCI Bus. The  
controller also has one serial port and four timers.  
1.2  
CPU Interface  
R
Features  
•
•
•
Connects directly to a 250 MHz V 5000 CPU.  
100 MHz CPU bus.  
Peak block-transfer throughput of 800 Mbytes/sec, maximum sustained  
throughput of 640 Mbytes/sec.  
•
•
•
•
16 x 8-byte (128-byte) CPU-to-controller FIFO.  
Little-endian or big-endian byte order on CPU interface.  
Supports secondary cache.  
15 interrupt sources, individually enabled and assigned to one of the CPU’s  
seven interrupt inputs.  
•
Supports all CPU bus-cycle types (but the only write type is pipelined write).  
Parity generation and checking on CPU data cycles.  
•
•
Mode data at reset provided by a serial EEPROM or by the controller.  
3.3V I/O.  
Memory Interface  
•
•
•
100 MHz memory bus.  
Maximum sustained throughput of 800 Mbytes/sec.  
Supports three physical loads per data bit: two SDRAM physical banks and  
one other (e.g., EPROM, Flash, or buffers bridging to a secondary memory  
bus).  
•
Supports four types of SDRAM with two to four on-chip virtual banks: 256Mb  
four-bank, 64Mb four-bank, 64Mb two-bank, 16Mb two-bank.  
•
•
•
•
On-chip bank-interleaving buffers.  
Programmable address ranges for each memory bank.  
Memory may maintain multiple open SDRAM pages.  
Parity or ECC generation and checking of memory data cycles with 64+8 bits  
of SDRAM and no performance degradation.  
1234567...224

中文翻译

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 		Resistor/Capacitor Network, RC NETWORK, TERMINATOR, 1W, 56ohm, 0.000033uF, SURFACE MOUNT,
VRC560K/470MT/R VISHAY

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VRC560K/470MTF VISHAY

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 		Resistor/Capacitor Network, RC NETWORK, TERMINATOR, 1W, 56ohm, 0.000047uF, SURFACE MOUNT,
VRC560K/800MT/R VISHAY

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 		Resistor/Capacitor Network, RC NETWORK, TERMINATOR, 1W, 56ohm, 0.00008uF, SURFACE MOUNT, S

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