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VP310CGGQ1N PDF预览

VP310CGGQ1N

更新时间： 2024-09-28 21:14:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 商用集成电路
页数 文件大小 规格书
3页 608K
描述
Consumer Circuit, PQFP80, MQFP-80

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中文翻译

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VP310CGGQ1N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QFP,Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-PQFP-G80
JESD-609代码：e0长度：14 mm
功能数量：1端子数量：80
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
认证状态：Not Qualified座面最大高度：2.45 mm
表面贴装：YES温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

VP310CGGQ1N 数据手册

 浏览型号VP310CGGQ1N的Datasheet PDF文件第2页浏览型号VP310CGGQ1N的Datasheet PDF文件第3页 
VP310  
Satellite Channel Demodulator  
Preliminary Information  
DS5155  
ISSUE 2.00  
May 2001  
The VP310 is a QPSK/BPSK 1 to 45 MBaud  
demodulator and channel decoder for digital satellite  
television transmissions to the European Broadcast  
Union ETS 300 421 specification. It receives analog  
I and Q signals from the tuner, digitises and digitally  
demodulates the signals, and implements the  
complete DVB/DSS FEC (Forward Error Correction),  
and de-scrambling function. The output is in the form  
of MPEG2 or DSS transport stream data packets.  
The VP310 also provides automatic gain control to  
the RF front-end devices.  
Ordering Information  
VP310 CG GQ1N  
•
•
•
Up to 15 MHz LNB frequency tracking  
Fully digital timing and phase recovery loops  
High level software interface for minimum  
development time  
2
The VP310 has a serial I C port interface to the  
•
DiSEqC™ v1.1: control outputs for full control  
of LNB and dish  
control microprocessor. Minimal software is required  
to control the VP310 because of the built in  
automatic search and decode control functions.  
Additional Features  
2
•
•
•
I C bus microprocessor interface  
Applications  
All digital clock and carrier recovery  
On-chip PLL clock generation using low cost 10  
to 15 MHz crystal  
3.3V operation  
80 pin MQFP package  
•
DVB 1 to 45 MBaud compliant satellite  
receivers  
•
•
•
DSS 20 MBaud compliant satellite receivers  
SCPC receivers (Single Channel Per Carrier)  
SMATV trans-modulators  
•
•
•
•
Low external component count  
Commercial temperature range 0 to 70°C  
(Single Master Antenna TV)  
•
•
LMDS (Local Multipoint Distribution Service)  
Satellite PC applications  
Demodulator  
•
BPSK or QPSK programmable  
Key Features  
•
Conforms to EBU specification for DVB-S and  
DirecTV specification for DSS  
Viterbi  
•
Programmable decoder rates 1/2, 2/3, 3/4, 5/6,  
6/7, 7/8  
•
On-chip digital filtering supports 1 to 45 MBaud  
Symbol rates  
•
•
•
Constraint length k=7  
Trace back depth 128  
Extensive SNR and BER monitors  
•
•
On-chip 6-bit 60 or 90 MHz dual-ADC  
High speed scanning mode for blind symbol  
rate and code rate acquisition  
MPEG/  
DSS  
Packets  
I I/P  
Timing recovery  
Matched filter  
Phase recovery  
DVB  
DSS  
FEC  
Decimation  
Filteriing  
Dual ADC  
De-rotator  
Q I/P  
Bus I/O  
Analog  
AGC  
control  
Acquisition  
Control  
I2C  
Interface  
Clock Generation  
Figure 1 - VP310 Functional Block Diagram  
1
123

中文翻译

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