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VP0120 PDF预览

VP0120

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
4页 57K
描述
P-Channel Enhancement-Mode Vertical DMOS FETs

VP0120 数据手册

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VP0120  
P-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Order Number / Package  
ID(ON)  
BVDSS  
/
RDS(ON)  
BVDGS  
(max)  
(min)  
TO-92  
Die†  
-200V  
25  
-100mA  
VP0120N3  
VP0120ND  
MIL visual screening available  
7
Features  
Advanced DMOS Technology  
These enhancement-mode (normally-off) transistors utilize a  
vertical DMOS structure and Supertex’s well-proven silicon-gate  
manufacturing process. This combination produces devices with  
the power handling capabilities of bipolar transistors and with the  
high input impedance and positive temperature coefficient inher-  
ent in MOS devices. Characteristic of all MOS structures, these  
devices are free from thermal runaway and thermally-induced  
secondary breakdown.  
Free from secondary breakdown  
Low power drive requirement  
Ease of paralleling  
9
Low CISS and fast switching speeds  
Excellent thermal stability  
Integral Source-Drain diode  
High input impedance and high gain  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where high breakdown  
voltage, high input impedance, low input capacitance, and fast  
switching speeds are desired.  
Complementary N- and P-channel devices  
Applications  
Motor controls  
Package Options  
Converters  
Amplifiers  
Switches  
Power supply circuits  
Drivers (relays, hammers, solenoids, lamps, memories,  
displays, bipolar transistors, etc.)  
S G D  
Absolute Maximum Ratings  
TO-92  
Drain-to-Source Voltage  
Drain-to-Gate Voltage  
Gate-to-Source Voltage  
BVDSS  
BVDGS  
± 20V  
Operating and Storage Temperature  
-55°C to +150°C  
300°C  
Soldering Temperature*  
Note: See Package Outline section for dimensions.  
* Distance of 1.6 mm from case for 10 seconds.  
7-223  

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