Datasheet > VN0120N2

VN0120N2

更新时间： 2024-01-22 00:59:17

品牌	Logo	应用领域
超科 - SUPERTEX		/
页数	文件大小	规格书
4页	57K
描述
N-Channel Enhancement-Mode Vertical DMOS FETs

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数据手册

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VN0120N2 数据手册

VP0120

P-Channel Enhancement-Mode

Vertical DMOS FETs

Ordering Information

Order Number / Package

I_D(ON)

BV_DSS

R_DS(ON)

BV_DGS

(max)

(min)

TO-92

Die^†

-200V

25Ω

-100mA

VP0120N3

VP0120ND

†

MIL visual screening available

Features

Advanced DMOS Technology

These enhancement-mode (normally-off) transistors utilize a

vertical DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces devices with

the power handling capabilities of bipolar transistors and with the

high input impedance and positive temperature coefficient inher-

ent in MOS devices. Characteristic of all MOS structures, these

devices are free from thermal runaway and thermally-induced

secondary breakdown.

■

Free from secondary breakdown

Low power drive requirement

Ease of paralleling

Low C_ISSand fast switching speeds

Excellent thermal stability

Integral Source-Drain diode

High input impedance and high gain

Supertex’s vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where high breakdown

voltage, high input impedance, low input capacitance, and fast

switching speeds are desired.

Complementary N- and P-channel devices

Applications

■

Motor controls

Package Options

Converters

Amplifiers

Switches

Power supply circuits

Drivers (relays, hammers, solenoids, lamps, memories,

displays, bipolar transistors, etc.)

S G D

Absolute Maximum Ratings

TO-92

Drain-to-Source Voltage

Drain-to-Gate Voltage

Gate-to-Source Voltage

BV_DSS

BV_DGS

± 20V

Operating and Storage Temperature

-55°C to +150°C

300°C

Soldering Temperature*

Note: See Package Outline section for dimensions.

* Distance of 1.6 mm from case for 10 seconds.

7-223

12 3 4

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