2N5564/5565/5566
Vishay Siliconix
Matched N-Channel JFET Pairs
PRODUCT SUMMARY
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Typ (pA) jVGS1 − VGS2j Max (mV)
2N5564
2N5565
2N5566
−0.5 to −3
−0.5 to −3
−0.5 to −3
−40
−40
−40
7.5
7.5
7.5
−3
−3
−3
5
10
20
FEATURES
BENEFITS
APPLICATIONS
D Two-Chip Design
D Tight Differential Match vs. Current
D Wideband Differential Amps
D High Slew Rate
D Improved Op Amp Speed, Settling Time
D High-Speed,
Accuracy
Temp-Compensated,
Single-Ended Input Amps
D High-Speed Comparators
D Impedance Converters
D Matched Switches
D Low Offset/Drift Voltage
D Low Gate Leakage: 3 pA
D Low Noise: 12 nV⁄√Hz @ 10 Hz
D Good CMRR: 76 dB
D Minimum Parasitics
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signals
D Maximum High Frequency Performance
DESCRIPTION
The 2N5564/5565/5566 are matched pairs of JFETs mounted
in a TO-71 package. This two-chip design reduces parasitics
for good performance at high frequency while ensuring
The hermetically-sealed TO-71 package is available with full
military processing (see Military Information).
extremely tight matching.
breakdown voltage (V(BR)DSS typically > 55 V), high gain
(typically > 9 mS), and <5 mV offset between the two die.
This series features high
For similar products see the low-noise U/SST401 series, and
the low-leakage 2N5196/5197/5198/5199 data sheets.
TO-71
S
G
2
1
1
3
6
4
D
1
D
2
2
5
G
1
S
2
Top View
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 V
Gate-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "80 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to 150_C
a
Power Dissipation :
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 325 mW
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
Notes
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . 300 _C
16
a. Derate 2.6 mW/_C above 25_C
b. Derate 5.2 mW/_C above 25_C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 200_C
Document Number: 70254
S-50150—Rev. E, 24-Jan-05
www.vishay.com
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