UNISONIC TECHNOLOGIES CO., LTD
VGA7S019
Preliminary
TVS DIODE
7-CHANNEL INTEGRATED
ESD SOLUTION FOR VGA
PORT WITH INTEGRATED
LEVEL SHIFTER AND
MATCHING IMPEDANCE
DESCRIPTION
The UTC VGA7S019 is an ESD solution for the VGA or DVI-I
port connector. This device integrates ESD protection for all
signals, level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the VIDEO, DDC and SYNC
lines is implemented with low-capacitance current steering
diodes.
Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with
low voltage video controller ICs to provide design flexibility in multi-supply-voltage environments.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC
(SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing
between Ground and VCC_SYNC, which is typically 5V. Additionally, each driver has a series termination resistor
(RT) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the
HSYNC and VSYNC lines of the video cable. At the SYNC output the UTC VGA7S019 offers 65-Ω, 55-Ω, or 15-Ω
series termination resistor option to match different transmission line impedances.
Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a
lower supply voltage than the monitor. The gate terminals for the MOSFETs (VCC_DDC) should be connected to the
supply rail (typically 3.3V) that supplies power to the transceivers of the DDC controller.
The UTC VGA7S019 confirms the IEC61000-4-2 (Level 4) system level ESD protection and ±15KV HBM ESD
protection. This device is offered in space-saving SSOP-16 packages.
FEATURES
* 7 Channels of ESD protection for all VGA port connector
pins meeting IEC-61000-4-2 Level 4 ESD requirements
(±8kV contact discharge)
* 5V drivers for HSYNC and VSYNC lines
* Very low loading capacitance from ESD protection
diodes on VIDEO lines (2.5pF)
* Integrated impedance matching resistors on sync lines:
–VGA7S019-15: 15Ω Termination
–VGA7S019-55: 55Ω Termination
* Bi-Directional level shifting N-Channel FETs
provided for DDC_CLK and DDC_DATA channels
* Flow-Through single-in-line pin mapping ensures no
additional board layout burden while placing the ESD
protection chip near the connector
–VGA7S019-65: 65Ω Termination
* Includes ESD protection, level-shifting, buffering and
sync impedance matching
www.unisonic.com.tw
1 of 7
Copyright © 2016 Unisonic Technologies Co., Ltd
QW-R223-024.c