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VES1993 PDF预览

VES1993

更新时间: 2024-09-23 22:16:11
品牌 Logo 应用领域
恩智浦 - NXP 消费电路商用集成电路
页数 文件大小 规格书
15页 123K
描述
SINGLE CHIP SATELLITE CHANNEL RECEIVER

VES1993 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:ALSO REQUIRES 5V SUPPLY商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PQFP-G100长度:20 mm
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
认证状态:Not Qualified座面最大高度:3.3 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

VES1993 数据手册

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VES 1993  
SINGLE CHIP  
SATELLITE  
CHANNEL RECEIVER  
FEATURES  
APPLICATIONS  
DSS and DVB-S compatible single chip  
demodulator & forward error correction.  
Dual 6-bit ADC on chip.  
DSS receivers.  
DVB-S receivers (ETS 300-421).  
Direct Broadcast Satellite (DBS).  
PLL for crystal frequency multiplication.  
Variable rate BPSK/QPSK coherent  
demodulator.  
DESCRIPTION  
The VES 1993 is a single-chip channel receiver for satellite television  
reception which matches both DSS and DVB-S standards. The  
device contains a dual 6-bit flash analog to digital converter, variable  
rate BPSK/QPSK coherent demodulator and Forward Error  
Correction functions.The ADCs directly interface with I and Q analog  
baseband signals. After A to D conversion, the VES 1993 implements  
a bank of cascadable filters as well as antialias and half-Nyquist  
filters. Analog AGC signal is generated by an amplitude estimation  
function. The VES 1993 performs clock recovery at twice the Baud  
rate and achieves coherent demodulation without any feedback to  
the local oscillator. Forward Error Correction is built around two error  
correcting codes : a Reed-Solomon (outer code), and a Viterbi  
decoder (inner code). The Reed-Solomon decoder corrects up to 8  
erroneous bytes among the N bytes of one data packet.  
Convolutional deinterleaver is located between the Viterbi output and  
the R.S. decoder input. De-interleaver and R.S. decoder are  
automatically synchronized thanks to the frame synchronisation  
algorithm which uses the sync pattern present in each packet. The  
VES 1993 is controlled via an I2C bus interface. The circuit operates  
up to 91MHz and can process variable modulation rates, up to  
45Mbaud.  
Modulation rate from 1 to 45MBaud.  
Automatic Gain Control output.  
Digital symbol timing recovery :  
Acquisition range up to ±240ppm  
Digital carrier recovery :  
Acquisition range up to ±12% of symbol rate  
Half Nyquist baseband filters on chip  
roll-off = 0.35 for DVB and 0.2 for DSS  
Channel quality estimation.  
Viterbi decoder :  
Supported rates : from 1/2 to 8/9.  
Constraint length K = 7  
with G1 = 1718 G2 = 1338  
VBER measurement provided.  
Convolutional deinterleaver and Reed  
Solomon decoder according to DVB and  
DSS specifications.  
Automatic Frame Synchronization.  
Selectable DVB-S descrambling.  
I2C bus interface.  
100-pin MQFP package.  
CMOS technology (0.35 µm 3.3V).  
The VES 1993 provides an interrupt line which can be programmed  
on either events or timing information.  
Designed in 0.35 CMOS technology and housed in a 100-MQFP  
package, the VES 1993 operates over the commercial temperature  
range.  
comatlas S.A., 30 rue du Chêne Germain, BP 814, 35518 CESSON-SEVIGNE Cedex, FRANCE  
Phone : +33 (0)2 99 27 55 55, Fax : +33 (0)2 99 27 55 27, Internet : www.comatlas.fr / VES 1993 rev 2.0 / Jan 99  

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