Datasheet > VDS6616A4A

VDS6616A4A

更新时间： 2022-11-25 22:25:01

品牌	Logo	应用领域
威刚科技 - ADATA		动态存储器
页数	文件大小	规格书
8页	559K
描述
Synchronous DRAM(1M X 16 Bit X 4 Banks)

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VDS6616A4A 数据手册

V-Data

VDS6616A4A

1M x 16 Bit x 4 Banks

Synchronous DRAM

General Description

Features

•JEDEC standard LVTTL 3.3V power supply

•MRS Cycle with address key programs

The VDS6616A4A are four-bank Synchronous

DRAMs organized as 1,048,576 words x 16 bits x 4

banks,

-CAS Latency (2 & 3)

Synchronous design allows precise cycle control

with the use of system clock I/O transactions are

possible on every clock cycle.

Range of operating frequencies, programmable

burst length and programmable latencies allow the

same device to be useful for a variety of high

bandwidth high performance memory system

applications

-Burst Length (1,2,3,8,& full page)

-Burst Type (sequential & Interleave)

•4 banks operation

•All inputs are sampled at the positive edge of

the system clock

•Burst Read single write operation

•Auto & Self refresh

•4096 refresh cycle

•DQM for masking

•Package:54-pins 400 mil TSOP-Type II

Ordering Information.

Part No.

Frequency

200Mhz

166Mhz

143Mhz

133Mhz

Interface

Package

VDS6616A4A-5

VDS6616A4A-6

VDS6616A4A-7

VDS6616A4A-7.5

LVTTL

400mil 54pin TSOPII

Pin Assignment

Vss

DQ0

DQ15

DDQ

VssQ

DQ1

DQ2

DQ14

DQ13

VDDQ

DQ3

DQ4

DQ12

DQ11

DDQ

VSSQ

DQ5

DQ6

DQ10

DQ9

SSQ

VDDQ

DQ7

DQ8

VSS

LDQM

/WE

/CAS

/RAS

/CS

UDQM

CLK

CKE

A11

BA0

BA1

A10/AP

VSS

54-pin plastic TSOP II 400 mil

Rev 1.1 April, 2001

12 3 4 5 6 7 8

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