V-Data
VDS6608A4A
2M x 8 Bit x 4 Banks
Synchronous DRAM
General Description
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
The VDS6608A4A are four-bank Synchronous
DRAMs organized as 2,097,152 words x 8 bits x 4
banks.
-CAS Latency (2 & 3)
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
133Mhz
Interface
LVTTL
Package
400mil 54pin TSOPII
VDS6608A4A-75
Pin Assignment
V
DD
1
2
Vss
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
DQ7
V
DDQ
3
Vss
NC
Q
4
NC
DQ1
5
DQ6
V
SSQ
6
VDDQ
NC
7
NC
DQ2
8
DQ5
V
DDQ
9
VSSQ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ3
DQ4
V
SSQ
VDDQ
NC
NC
V
DD
VSS
NC
NC/RFU
DQM
CK
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
CKE
NC
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
VSS
54-pin plastic TSOP II 400 mil
Rev 1 April, 2001
1