PRELIMINARY
V62C5181024
MOSEL VITELIC
128K X 8 STATIC RAM
■ Packages
Features
– 32-pin TSOP (Standard)
– 32-pin 600 mil PDIP
– 32-pin 440 mil SOP (525 mil pin-to-pin)
■ High-speed: 35, 70 ns
■ Ultra low DC operating current of 5mA (max.)
TTL Standby: 5 mA (Max.)
CMOS Standby: 60 µA (Max.)
■ Fully static operation
Description
■ All inputs and outputs directly compatible
■ Three state outputs
The V62C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. It is built with MOSEL VITELIC’s
high performance CMOS process. Inputs and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures.
■ Ultra low data retention current (V = 2V)
CC
■ Single 5V ± 10% Power Supply
Functional Block Diagram
A0
VCC
GND
Row
1024 x 1024
Decoder
Memory Array
A9
I/O0
Column I/O
Input
Data
Circuit
Column Decoder
I/O7
A10
A16
CE1
CE2
OE
Control
Circuit
5181024 01
WE
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
•
W
•
P
•
35
•
70
•
L
•
LL
•
0°C to 70 °C
Blank
I
–40°C to +85°C
•
•
•
•
•
•
•
V62C5181024 Rev. 2.2 February 2000
1