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V62/18605-01XE PDF预览

V62/18605-01XE

更新时间: 2024-11-19 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路闪存
页数 文件大小 规格书
167页 2698K
描述
具有 60MHz 频率、128KB 闪存、CLA 的 C2000™ 增强型产品 32 位 MCU | PN | 80 | -55 to 125

V62/18605-01XE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LQFP-80
Reach Compliance Code:compliant风险等级:5.76
具有ADC:YES地址总线宽度:
位大小:32最大时钟频率:30 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G80
JESD-609代码:e4长度:12 mm
湿度敏感等级:3I/O 线路数量:45
端子数量:80片上程序ROM宽度:16
最高工作温度:125 °C最低工作温度:-55 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCHRAM(字节):20480
ROM(单词):65536ROM可编程性:FLASH
座面最大高度:1.6 mm速度:60 MHz
最大供电电压:1.995 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:12 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

V62/18605-01XE 数据手册

 浏览型号V62/18605-01XE的Datasheet PDF文件第2页浏览型号V62/18605-01XE的Datasheet PDF文件第3页浏览型号V62/18605-01XE的Datasheet PDF文件第4页浏览型号V62/18605-01XE的Datasheet PDF文件第5页浏览型号V62/18605-01XE的Datasheet PDF文件第6页浏览型号V62/18605-01XE的Datasheet PDF文件第7页 
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TMS320F28030, TMS320F28031, TMS320F28032  
TMS320F28033, TMS320F28034, TMS320F28035  
SPRS584N APRIL 2009REVISED JUNE 2020  
TMS320F2803x Microcontrollers  
1 Device Overview  
1.1 Features  
1
• High-efficiency 32-bit CPU (TMS320C28x)  
– 60 MHz (16.67-ns cycle time)  
• Code-security module  
• 128-bit security key and lock  
– Protects secure memory blocks  
– Prevents firmware reverse engineering  
• Serial port peripherals  
– 16 × 16 and 32 × 32 MAC operations  
– 16 × 16 dual MAC  
– Harvard bus architecture  
– Atomic operations  
– One Serial Communications Interface (SCI)  
Universal Asynchronous Receiver/Transmitter  
(UART) module  
– Two Serial Peripheral Interface (SPI) modules  
– One Inter-Integrated-Circuit (I2C) module  
– One Local Interconnect Network (LIN) module  
– Fast interrupt response and processing  
– Unified memory programming model  
– Code-efficient (in C/C++ and Assembly)  
• Programmable Control Law Accelerator (CLA)  
– 32-bit floating-point math accelerator  
– Executes code independently of the main CPU  
• Endianness: Little endian  
– One Enhanced Controller Area Network (eCAN)  
module  
• Enhanced control peripherals  
– ePWM  
• JTAG boundary scan support  
– IEEE Standard 1149.1-1990 Standard Test  
Access Port and Boundary Scan Architecture  
• Low cost for both device and system:  
– Single 3.3-V supply  
– High-Resolution PWM (HRPWM)  
– Enhanced Capture (eCAP) module  
– High-Resolution Input Capture (HRCAP) module  
– Enhanced Quadrature Encoder Pulse (eQEP)  
module  
– Analog-to-Digital Converter (ADC)  
– On-chip temperature sensor  
– Comparator  
– No power sequencing requirement  
– Integrated power-on reset and brown-out reset  
– Low power  
– No analog support pins  
• Clocking:  
• Advanced emulation features  
– Analysis and breakpoint functions  
– Real-time debug through hardware  
• Package options  
– 56-Pin RSH Very Thin Quad Flatpack (No lead)  
(VQFN)  
– 64-Pin PAG Thin Quad Flatpack (TQFP)  
– 80-Pin PN Low-Profile Quad Flatpack (LQFP)  
• Temperature options  
– Two internal zero-pin oscillators  
– On-chip crystal oscillator and external clock  
input  
– Watchdog timer module  
– Missing clock detection circuitry  
• Up to 45 individually programmable, multiplexed  
GPIO pins with input filtering  
• Peripheral Interrupt Expansion (PIE) block that  
supports all peripheral interrupts  
– T: –40°C to 105°C  
• Three 32-bit CPU timers  
– S: –40°C to 125°C  
– Q: –40°C to 125°C  
• Independent 16-bit timer in each Enhanced Pulse  
Width Modulator (ePWM)  
(AEC Q100 qualification for automotive  
applications)  
• On-chip memory  
– Flash, SARAM, OTP, Boot ROM available  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 

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