Datasheet > V62/18602-01XB

V62/18602-01XB

更新时间： 2024-11-19 11:12:23

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
103页	2259K
描述
温度范围为 -55°C 至 105°C 且符合 JESD204B 标准的超低噪声时钟抖动消除器 \| NKD \| 64

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LMK04828-EP

SNAS703 –APRIL 2017

LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1 Features

2 Applications

•

EP Features

•

Wireless Infrastructure

Data Converter Clocking

–

Gold Bondwires

Networking, SONET/SDH, DSLAM

Medical / Video / Military / Aerospace

Test and Measurement

Temperature Range: –55 to +105 °C

Lead Finish SnPb

•

Maximum Distribution Frequency: 3.2 GHz

JESD204B Support

3 Description

The LMK04828-EP device is the industry's highest

performance clock conditioner with JESD204B

support.

Ultra-Low RMS Jitter

–

88-fs RMS Jitter (12 kHz to 20 MHz)

91-fs RMS Jitter (100 Hz to 20 MHz)

–162.5 dBc/Hz Noise Floor at 245.76 MHz

The 14 clock outputs from PLL2 can be configured to

drive seven JESD204B converters or other logic

devices using device and SYSREF clocks. SYSREF

can be provided using both DC and AC coupling. Not

limited to JESD204B applications, each of the 14

outputs can be individually configured as high-

performance outputs for traditional clocking systems.

•

Up to 14 Differential Device Clocks From PLL2

–

Up to 7 SYSREF Clocks

Maximum Clock Output Frequency 3.2 GHz

LVPECL, LVDS, HSDS, LCPECL

Programmable Outputs From PLL2

•

Up to 1 Buffered VCXO/Crystal Output From PLL1

LVPECL, LVDS, 2xLVCMOS Programmable

The high performance combined with features like the

ability to trade off between power or performance,

dual VCOs, dynamic digital delay, holdover, and

glitchless analog delay make the LMK04828-EP ideal

for providing flexible high-performance clocking trees.

–

Multi-Mode: Dual PLL, Single PLL, and Clock

Distribution

•

Dual Loop PLLatinum™ PLL Architecture

PLL1

Device Information⁽¹⁾

PART

NUMBER

VCO0

FREQUENCY

–

Up to 3 Redundant Input Clocks

VCO1 FREQUENCY

–

Automatic and Manual Switchover Modes

Hitless Switching and LOS

LMK04828-EP

2450 to 2755 MHz

2875 to 3080 MHz

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

Integrated Low-Noise Crystal Oscillator Circuit

Holdover Mode When Input Clocks are Lost

Simplified Schematic

•

PLL2

Multiple —clean“

clocks at different

frequencies

–

Normalized [1 Hz] PLL Noise Floor of

–227 dBc/Hz

Crystal or

OSCout

LMX2582

VCXO

Recovered

—dirty“ clock or

clean clock

–

Phase Detector Rate up to 155 MHz

OSCin Frequency-Doubler

Two Integrated Low-Noise VCOs

PLL+VCO

CLKin0

DCLKout12

Backup

Reference

Clock

FPGA

SDCLKout13

LMK04828-EP

CLKin1

DCLKout8 &

DCLKout10

50% Duty Cycle Output Divides, 1 to 32

(Even and Odd)

SDCLKout9 &

SDCLKout11

DCLKout0 &

DCLKout2

•

Precision Digital Delay, Dynamically Adjustable

25-ps Step Analog Delay

DCLKout4,

SDCLKout5

D_DA_AC_C

ADC

SDCLKout1 &

SDCLKout3

Serializer/

Deserializer

3.15-V to 3.45-V Operation

Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8

mm)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...103

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