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V62/12624-01XE PDF预览

V62/12624-01XE

更新时间： 2024-02-27 22:36:09
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动逻辑集成电路时钟驱动器
页数 文件大小 规格书
15页 618K
描述
具有可选输入的 HiRel、1:10 LVPECL 缓冲器 | VF | 32 | -55 to 125

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V62/12624-01XE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP, QFP32,.35SQ,32针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.75
系列：CDC输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQFP-G32JESD-609代码：e4
长度：7 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
最大I（ol）：0.005 A湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：32实输出次数：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：+-2.5/+-3.3 V
最大电源电流（ICC）：85 mAProp。Delay @ Nom-Sup：0.355 ns
传播延迟（tpd）：0.355 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：1.6 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.8 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
最小 fmax：3500 MHzBase Number Matches：1

V62/12624-01XE 数据手册

 浏览型号V62/12624-01XE的Datasheet PDF文件第2页浏览型号V62/12624-01XE的Datasheet PDF文件第3页浏览型号V62/12624-01XE的Datasheet PDF文件第4页浏览型号V62/12624-01XE的Datasheet PDF文件第5页浏览型号V62/12624-01XE的Datasheet PDF文件第6页浏览型号V62/12624-01XE的Datasheet PDF文件第7页 
CDCLVP111  
www.ti.com  
SCAS859D –JANUARY 2009–REVISED MARCH 2010  
LOW-VOLTAGE 1:10 LVPECL  
WITH SELECTABLE INPUT CLOCK DRIVER  
Check for Samples: CDCLVP111  
1
FEATURES  
APPLICATIONS  
•
•
Designed for Driving 50 Ω Transmission Lines  
High Performance Clock Distribution  
2
•
Distributes One Differential Clock Input Pair  
LVPECL to 10 Differential LVPECL  
•
•
Fully Compatible With LVECL/LVPECL  
LQFP AND QFN PACKAGE  
(TOP VIEW)  
Supports a Wide Supply Voltage Range From  
2.375 V to 3.8 V  
•
•
Selectable Clock Input Through CLK_SEL  
Low-Output Skew (Typ 15 ps) for  
Clock-Distribution Applications  
–
–
–
–
Additive Jitter Less Than 1 ps  
Propagation Delay Less Than 350 ps  
Open Input Default State  
PowerPAD  
(0)  
LVDS, CML, SSTL input compatible  
•
VBB Reference Voltage Output for  
Single-Ended Clocking  
•
•
•
Available in a 32-Pin LQFP and QFN Package  
Frequency Range From DC to 3.5 GHz  
Pin-to-Pin Compatible With MC100 Series  
EP111, ES6111, LVEP111, PTN1111  
DESCRIPTION  
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of  
differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can  
accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω  
transmission lines. When an output pin is not used, leaving it open is recommended to reduce power  
consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically  
terminated to 50 Ω.  
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin  
should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.  
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.  
The CDCLVP111 is characterized for operation from –40°C to 85°C.  
Table 1. FUNCTION TABLE  
CLK_SEL  
ACTIVE CLOCK INPUT  
CLK0, CLK0  
0
1
CLK1, CLK1  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
 
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