SM320DM642-EP
Video/Imaging Fixed Point Digital Signal Processor
www.ti.com
SGUS058B–JUNE 2007–REVISED JANUARY 2008
1 SM320DM642 Video/Imaging Fixed-Point Digital Signal Processor
1.1 Features
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VelociTI.2™ Increased Orthogonality
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Controlled Baseline
One Assembly/Test/Fabrication Site
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L1/L2 Memory Architecture
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128K Bit (16K Byte) L1P Program Cache
(Direct Mapped)
128K Bit (16K Byte) L1D Data Cache (2-Way
Set-Associative)
2M Bit (256K Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
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Enhanced Diminishing Manufacturing Sources
(DMS) Support
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Enhanced Product-Change Notification
Qualification Pedigree(1)
High-Performance Digital Media Processor
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2 ns, 1.67 ns, 1.39 ns Instruction Cycle
Time
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Endianess: Little Endian, Big Endian
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500 MHz, 600 MHz, 720 MHz Clock Rate
(500/600 MHz devices are product preview
only)
64 Bit External Memory Interface (EMIF)
Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM, SBSRAM,
ZBT SRAM, and FIFO)
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Eight 32-Bit Instructions/Cycle
4000 MIPS, 4800 MIPS, 5760 MIPS
Fully Software-Compatible With C64x™
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1024M-Byte Total Addressable External
Memory Space
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VelociTI.2™ Extensions to VelociTI™
Advanced Very Long Instruction Word (VLIW)
TMS320C64x™ DSP Core
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
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Eight Highly Independent Functional Units
With VelociTI.2™ Extensions:
10/100 Mbps Ethernet MAC (EMAC)
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IEEE 802.3 Compliant
Media Independent Interface (MII)
Eight Independent Transmit (TX) Channels
and One Receive (RX) Channel
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Six ALUs (32/40 Bit), Each Supports
Single 32 Bit, Dual 16 Bit, or Quad 8 Bit
Arithmetic per Clock Cycle
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Two Multipliers Support Four 16 × 16-Bit
Multiplies (32 Bit Results) per Clock
Cycle or Eight 8 × 8 Bit Multiplies (16 Bit
Results) per Clock Cycle
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Management Data Input/Output (MDIO)
Three Configurable Video Ports
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Provide a Glueless I/F to Common Video
Decoder and Encoder Devices
Supports Multiple Resolutions/Video Stds
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Load-Store Architecture With Non-Aligned
Support
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64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
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VCXO Interpolated Control Port (VIC)
Supports Audio/Video Synchronization
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Host Port Interface (HPI) [32/16 Bit]
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Instruction Set Features
32 Bit/66 MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
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Byte Addressable (8/16/32/64 Bit Data)
8-Bit Overflow Protection
Bit Field Extract, Set, Clear
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Multichannel Audio Serial Port (McASP)
Normalization, Saturation, Bit-Counting
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Eight Serial Data Pins
Wide Variety of I2S and Similar Bit Stream
Format
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
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Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
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Inter-Integrated Circuit (I2C Bus™)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C64x, VelociTI.2, VelociTI, TMS320C64x, C6000, TMS320C6000, DM64x, C62x, TMS320C62x, TMS320C67x, Code Composer Studio,
DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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