Datasheet > V62/06677-02XE

V62/06677-02XE

更新时间： 2023-09-03 20:26:57

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
27页	886K
描述
增强型产品 100Mbps 至 660Mbps、1:10 LVDS 串行器/解串器接收器 \| DB \| 28 \| -55 to 125

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数据手册

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V62/06677-02XE 数据手册

SN65LV1023A-EP

SN65LV1224B-EP

www.ti.com

SGLS358–SEPTEMBER 2006

10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

FEATURES

•

100-Mbps to 660-Mbps Serial LVDS Data

Payload Bandwidth at 10-MHz to 66-MHz

System Clock

•

Controlled Baseline

– One Assembly/Test Site, One Fabrication

Site

•

Pin-Compatible Superset of

DS92LV1023/DS92LV1224

•

Extended Temperature Performance of –55°C

to 125°C

Chipset (Serializer/Deserializer) Power

Consumption <450 mW (Typ) at 66 MHz

Enhanced Diminishing Manufacturing

Sources (DMS) Support

•

Synchronization Mode for Faster Lock

Lock Indicator

•

Enhanced Product-Change Notification

(1)

No External Components Required for PLL

Qualification Pedigree

28-Pin SSOP and Space Saving 5 × 5 mm

QFN Packages Available

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

•

Programmable Edge Trigger on Clock

Flow-Through Pinout for Easy PCB Layout

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

DESCRIPTION

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to

transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz

to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload

encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC

patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,

the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is

available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –55°C to

125°C.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

SN65LV1023AMDBREP

SN65LV1224BMDBREP

TOP-SIDE MARKING

LV1023AMEP

-55°C to 125°C

SSOP - DB

Reel of 2000

LV1224BMEP

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...27

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与V62/06677-02XE相关器件

型号	品牌	获取价格	描述	数据表
V62/06678-01XE	TI	获取价格	具有施密特触发输入的增强型产品单路 0.8V 至 2.7V 高速反相器 \| DBV \| 5
V62/06679-01XE	TI	获取价格	20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
V62/07603-01XE	TI	获取价格	QUADRUPLE DIFFERENTIAL LINE RECEIVER
V62/07604-01XE	TI	获取价格	NANOPOWER 1.8-V SOT23 COMPARATORS WITH VOLTAGE REFERENCE
V62/07605-01XE	TI	获取价格	HiRel Enhanced Product, dual, 30-V, 700-kHz operational amplifier \| D \| 8 \| -55 to 125
V62/07606-01XE	TI	获取价格	DUAL HIGH-SPEED LOW-NOISE OPERATIONAL AMPLIFIER
V62/07607-01XE	TI	获取价格	12 位 500MSPS 模数转换器 (ADC) - 增强型产品 \| PFP \| 80 \|
V62/07608-01XE	TI	获取价格	EMC OPTIMIZED CAN TRANSCEIVER
V62/07609-01XE	TI	获取价格	ISOLATED FEEDBACK GENERATOR
V62/07610-01XE	TI	获取价格	DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP S

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