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V62/05623-01XE

更新时间： 2023-06-19 15:34:52
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
9页 126K
描述
增强型产品 2 通道、2 输入、1.65V 至 5.5V 与非门 | DCT | 8 | -55 to 115

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V62/05623-01XE 数据手册

 浏览型号V62/05623-01XE的Datasheet PDF文件第2页浏览型号V62/05623-01XE的Datasheet PDF文件第3页浏览型号V62/05623-01XE的Datasheet PDF文件第4页浏览型号V62/05623-01XE的Datasheet PDF文件第5页浏览型号V62/05623-01XE的Datasheet PDF文件第6页浏览型号V62/05623-01XE的Datasheet PDF文件第7页 
SN74LVC2G00W-EP  
DUAL 2-INPUT POSITIVE-NAND GATE  
www.ti.com  
SCES645–SEPTEMBER 2005  
FEATURES  
•
Controlled Baseline  
•
•
±24-mA Output Drive at 3.3 V  
– One Assembly/Test Site, One Fabrication  
Site  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
•
Extended Temperature Performance of –55°C  
to 115°C  
•
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
•
•
Enhanced Product-Change Notification  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
(1)  
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
Supports 5-V VCC Operation  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.3 ns at 3.3 V  
Low Power Consumption, 10-µA Max ICC  
DCT PACKAGE  
(TOP VIEW)  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
1A  
1B  
2Y  
V
CC  
1
2
3
4
8
7
6
5
1Y  
2B  
2A  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
GND  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC2G00W-EP performs the Boolean function Y = A • B or Y = A + B in positive logic.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
–55°C to 115°C  
SSOP – DCT  
Reel of 3000  
SN74LVC2G00WDCTREP  
C00_ _ _  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...9

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V62/05623-01XE 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC2G00WDCTREP TI

完全替代

 DUAL 2-INPUT POSITIVE-NAND GATE
SN74LVC2G00DCT TI

类似代替

 LVC/LCX/Z SERIES, DUAL 2-INPUT NAND GATE, PDSO8, PLASTIC, TSSOP-8
SN74LVC2G00DCTR TI

类似代替

 DUAL 2 INPUT POSITIVE NAND GATE

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