Datasheet > V62/05607-06YA

V62/05607-06YA

更新时间： 2024-11-19 11:06:19

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
130页	1802K
描述
增强型产品 C6416T 定点 DSP \| GLZ \| 532 \| -40 to 105

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

V62/05607-06YA 数据手册

ꢀꢁ ꢂ ꢃ ꢄꢅꢆ ꢇꢅ ꢈꢉ ꢊꢋ

ꢌ ꢍꢎ ꢊꢏꢐꢋꢑ ꢍ ꢒꢈ ꢏꢍ ꢓꢍ ꢈꢔꢕ ꢀꢍ ꢓ ꢒꢔꢕ ꢋꢖ ꢑ ꢄꢊ ꢀ ꢀꢑ ꢖ

SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006

ꢀ

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

ꢀ

Two External Memory Interfaces (EMIFs)

− One 64-Bit (EMIFA), One 16-Bit (EMIFB)

− Glueless Interface to Asynchronous

Memories and Synchronous Memories

− 1280M-Byte Total Addressable External

Memory Space

ꢀ

Extended Temperature Performance of up

to −40°C to 105°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

ꢀ

Instruction Set Features

− Byte-Addressable (8-/16-/32-/64-Bit Data)

− 8-Bit Overflow Protection

− Bit-Field Extract, Set, Clear

− Normalization, Saturation, Bit-Counting

− VelociTI.2 Increased Orthogonality

Enhanced Product-Change Notification

†

Qualification Pedigree

Highest-Performance Fixed-Point DSPs

− 1.67-/1.39-/1.17-/1-ns Instruction Cycle

− 600-/720-/850-MHz, 1-GHz Clock Rate

− Eight 32-Bit Instructions/Cycle

− Twenty-Eight Operations/Cycle

− 4800, 5760, 6800, 8000 MIPS

ꢀ

Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

Host-Port Interface (HPI)

− User-Configurable Bus Width (32-/16-Bit)

− Fully Software-Compatible With C62x

− C6414/15/16 Devices Pin-Compatible

32-Bit/33-MHz, 3.3-V PCI Master/Slave

Interface Conforms to PCI Specification 2.2

− Three PCI Bus Address Registers

− Four-Wire Serial EEPROM Interface

− PCI Interrupt Request Under DSP

Program Control

ꢀ

VelociTI.2 Extensions to VelociTI

Advanced Very-Long-Instruction-Word

(VLIW) TMS320C64x DSP Core

− Eight Highly Independent Functional

Units With VelociTI.2 Extensions

− Non-Aligned Load-Store Architecture

− 64 32-Bit General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

− DSP Interrupt Via PCI I/O Cycle

ꢀ

Three Multichannel Buffered Serial Ports

− Direct Interface to T1/E1, MVIP, SCSA

Framers

− Up to 256 Channels Each

ꢀ

VCP

− ST-Bus-Switching-, AC97-Compatible

− Serial Peripheral Interface (SPI)

Compatible (Motorola)

− Supports Over 833 7.95-Kbps AMR

− Programmable Code Parameters

TCP

ꢀ

Three 32-Bit General-Purpose Timers

− Supports up to 10 2-Mbps or

60 384-Kbps 3GPP (6 Iterations)

− Programmable Turbo Code and

Decoding Parameters

UTOPIA [C6416T]

− UTOPIA Level 2 Slave ATM Controller

− 8-Bit Transmit and Receive Operations

up to 50 MHz per Direction

ꢀ

L1/L2 Memory Architecture

− 128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped)

− 128K-Bit (16K-Byte) L1D Data Cache

(2-Way Set-Associative)

− User-Defined Cell Format up to 64 Bytes

ꢀ

16 General-Purpose I/O (GPIO) Pins

‡

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

− 8M-Bit (1024K-Byte) L2 Unified Mapped

RAM/Cache (Flexible Allocation)

ꢀ

532-Pin Ball Grid Array (BGA) Package

(GLZ Suffix), 0,8-mm Ball Pitch

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

†

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.

This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this

component beyond specified performance and environmental limits.

‡

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

ꢈ

ꢗ

ꢘ

ꢙ

ꢚ

ꢛ

ꢜ

ꢝ

ꢞ

ꢟ

ꢠ

ꢡ

ꢜ

ꢛ

ꢠ

ꢡ

ꢢ

ꢘ

ꢠ

ꢙ

ꢘ

ꢠ

ꢣ

ꢛ

ꢤ

ꢞ

ꢢ

ꢡ

ꢘ

ꢛ

ꢠ

ꢛ

ꢠ

ꢥ

ꢤ

ꢛ

ꢚ

ꢝ

ꢜ

ꢡ

ꢛꢣ ꢚꢟ ꢦ ꢟ ꢧ ꢛꢥ ꢞꢟ ꢠ ꢡꢨ ꢈꢗ ꢟ ꢙ ꢡ ꢢ ꢡꢝꢙ ꢛꢣ ꢟꢢ ꢜ ꢗ ꢚꢟ ꢦꢘꢜ ꢟ ꢘꢙ ꢘꢠꢚ ꢘꢜꢢ ꢡꢟ ꢚ ꢛꢠ ꢡꢗ ꢟ ꢥꢢ ꢩꢟꢪ ꢙꢫ

ꢙ

ꢘ

ꢠ

ꢞ

ꢛ

ꢤ

ꢟ

ꢡ

ꢗ

ꢢ

ꢠ

ꢛ

ꢠ

ꢟ

ꢥ

ꢗ

ꢢ

ꢙ

ꢟ

ꢙ

ꢥ

ꢟ

ꢜ

ꢘ

ꢣ

ꢬ

ꢘ

ꢠ

ꢩ

ꢘ

ꢡ

ꢙ

ꢟ

ꢧ

ꢟ

ꢜ

ꢡ

ꢤ

ꢘ

ꢜ

ꢢ

ꢧ

ꢜ

ꢗ

ꢢ

ꢤ

ꢢ

ꢜ

ꢡ

ꢟ

ꢤ

ꢘ

ꢙ

ꢡ

ꢘ

ꢜ

ꢙ

ꢨ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...130

中文翻译

下载PDF

与V62/05607-06YA相关器件

型号	品牌	获取价格	描述	数据表
V62/05608-02YE	TI	获取价格	WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS
V62/05608-03YE	TI	获取价格	WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS
V62/05610-01YE	TI	获取价格	LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE VOLTAGE FEEDBACK AMPLIFIER
V62/05611-01YE	TI	获取价格	Enhanced product, quad, 16-V, 3-MHz, RRIO operational amplifier \| D \| 14 \| -55 to 125
V62/05611-03TE	TI	获取价格	Enhanced product, single, 16-V, 3-MHz, RRIO operational amplifier \| DBV \| 5 \| -55 to 125
V62/05612-01XE	TI	获取价格	16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS
V62/05612-01YE	TI	获取价格	16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS
V62/05612-02YE	TI	获取价格	16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS
V62/05613-01XE	TI	获取价格	14 位、125MSPS 模数转换器 (ADC) - 增强型产品 \| PAP \| 64 \|
V62/05613-02XE	TI	获取价格	14 位、125MSPS 模数转换器 (ADC) - 增强型产品 \| PAP \| 64 \|

与V62/05607-06YA相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

36

产品中心

服务支持

精选活动

关于我们

帮助中心

V62/05607-06YA

V62/05607-06YA 数据手册

与V62/05607-06YA相关器件

与V62/05607-06YA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

V62/05607-06YA

V62/05607-06YA 数据手册

与V62/05607-06YA相关器件

与V62/05607-06YA相关文章

您还可以找

您在本页遇到什么问题？