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V62/04662-01YE

更新时间： 2024-01-16 03:08:51
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
14页 598K
描述
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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V62/04662-01YE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.42
控制类型：ENABLE LOW/HIGH系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：7.5 ns传播延迟（tpd）：9.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：4.4 mm

V62/04662-01YE 数据手册

 浏览型号V62/04662-01YE的Datasheet PDF文件第2页浏览型号V62/04662-01YE的Datasheet PDF文件第3页浏览型号V62/04662-01YE的Datasheet PDF文件第4页浏览型号V62/04662-01YE的Datasheet PDF文件第5页浏览型号V62/04662-01YE的Datasheet PDF文件第6页浏览型号V62/04662-01YE的Datasheet PDF文件第7页 
SN74LVC373A-EP  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS737C–NOVEMBER 2003–REVISED MARCH 2007  
FEATURES  
•
Controlled Baseline  
•
•
•
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
–
One Assembly/Test Site, One Fabrication  
Site  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
•
•
Extended Temperature Performance of –40°C  
to 125°C and –55°C to 125°C  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
VCC  
)
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
DB, DW OR PW PACKAGE  
(TOP VIEW)  
OE  
1Q  
1D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
•
•
•
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.5 ns at 3.3 V  
8Q  
8D  
7D  
7Q  
2D  
2Q  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
3Q  
15 6Q  
14  
13  
12  
11  
3D  
4D  
6D  
5D  
5Q  
LE  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
4Q  
GND  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q  
outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN74LVC373A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION(1)  
TA  
–40°C to 125°C  
–55°C to 125°C  
PACKAGE(2)  
ORDERABLE PART NUMBER  
SN74LVC373AQDWREP  
SN74LVC373AQPWREP  
SN74LVC373AMDBREP  
TOP-SIDE MARKING  
C373AEP  
SOIC – DW  
TSSOP – PW  
SSOP – DB  
Reel of 2000  
Reel of 2000  
Reel of 2000  
C373AEP  
C373AEP  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

中文翻译

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V62/04662-01YE 替代型号

型号 品牌 替代类型 描述 数据表
CLVC373AQPWRG4Q1 TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC373AQPWRQ1 TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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