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V62/04656-02YE PDF预览

V62/04656-02YE

更新时间: 2024-11-20 12:47:19
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 530K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

V62/04656-02YE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.14
Is Samacsys:N控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:5.8 ns
传播延迟(tpd):12.3 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:3.91 mmBase Number Matches:1

V62/04656-02YE 数据手册

 浏览型号V62/04656-02YE的Datasheet PDF文件第2页浏览型号V62/04656-02YE的Datasheet PDF文件第3页浏览型号V62/04656-02YE的Datasheet PDF文件第4页浏览型号V62/04656-02YE的Datasheet PDF文件第5页浏览型号V62/04656-02YE的Datasheet PDF文件第6页浏览型号V62/04656-02YE的Datasheet PDF文件第7页 
SN74LVC125A-EP  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS739CDECEMBER 2003REVISED DECEMBER 2006  
FEATURES  
Controlled Baseline  
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
One Assembly/Test Site, One Fabrication  
Site  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
ESD Protection Exceeds JESD 22  
Enhanced Product-Change Notification  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
(1)  
Qualification Pedigree  
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.8 ns at 3.3 V  
1000-V Charged-Device Model (C101)  
PW PACKAGE  
(TOP VIEW)  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
4OE  
4A  
4Y  
3OE  
3A  
3Y  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
1Y  
2OE  
2A  
2Y  
GND  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
8
DESCRIPTION/ORDERING INFORMATION  
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
C125AEP  
–40°C to 85°C  
TSSOP – PW  
TSSOP – PW  
SOIC – D  
Reel of 2000  
SN74LVC125AIPWREP  
Reel of 2000  
Reel of 2500  
SN74LVC125AMPWREP(2)  
SN74LVC125AMDREP  
125AMEP  
125AMEP  
–55°C to 125°C  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) Product Preview  
FUNCTION TABLE  
(EACH BUFFER)  
INPUTS  
OUTPUT  
Y
OE  
L
A
H
L
H
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

V62/04656-02YE 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC125AMDREP TI

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Enhanced Product Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -55 to 125
SN74LVC125AQDRQ1 TI

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QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC125ADBR TI

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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