Datasheet > 微控制器和处理器 > 数字信号处理器> V62/04649-01XA

V62/04649-01XA

更新时间： 2024-11-20 12:21:47

品牌	Logo	应用领域
德州仪器 - TI		微控制器和处理器外围集成电路数字信号处理器时钟
页数	文件大小	规格书
78页	1044K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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技术参数
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V62/04649-01XA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LFBGA, BGA144,13X13,32	针数：	144
Reach Compliance Code：	not_compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.92
其他特性：	ALSO REQUIRES 3.3V SUPPLY	地址总线宽度：	23
桶式移位器：	YES	位大小：	16
边界扫描：	YES	最大时钟频率：	20 MHz
外部数据总线宽度：	16	格式：	FIXED POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	S-PBGA-B144
JESD-609代码：	e0	长度：	12 mm
低功率模式：	YES	湿度敏感等级：	3
端子数量：	144	最高工作温度：	100 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA144,13X13,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	220	电源：	1.8,3.3 V
认证状态：	Not Qualified	RAM（字数）：	32768
座面最大高度：	1.4 mm	子类别：	Digital Signal Processors
最大供电电压：	1.98 V	最小供电电压：	1.71 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	12 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

V62/04649-01XA 数据手册

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SGUS046 − JULY 2003

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

Block-Memory-Move Instructions for Better

Program and Data Management

Instructions With a 32-Bit Long Word

Operand

Extended Temperature Performance of

−40°C to 100°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Instructions With Two- or Three-Operand

Reads

Arithmetic Instructions With Parallel Store

and Parallel Load

Enhanced Product-Change Notification

†

Qualification Pedigree

Conditional Store Instructions

Fast Return From Interrupt

Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

On-Chip Peripherals

− Software-Programmable Wait-State

Generator and Programmable Bank

Switching

− On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

− Three Multichannel Buffered Serial Ports

(McBSPs)

− Enhanced 8-Bit Parallel Host-Port

Interface With 16-Bit Data/Addressing

− One 16-Bit Timer

40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

− Six-Channel Direct Memory Access

(DMA) Controller

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

Data Bus With a Bus-Holder Feature

‡

IEEE Std 1149.1 (JTAG) Boundary Scan

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program

Space

Logic

10-ns Single-Cycle Fixed-Point Instruction

Execution Time (100 MIPS) for 3.3-V Power

Supply (1.8-V Core)

16K x 16-Bit On-Chip ROM

32K x 16-Bit Dual-Access On-Chip RAM

Available in a 144-Pin Ball Grid Array (BGA)

(GGU Suffix)

Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview

(literature number SPRU307).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

‡

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.

This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this

component beyond specified performance and environmental limits.

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

12 3 4 5 6 7...78

中文翻译

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与V62/04649-01XA相关器件

型号	品牌	获取价格	描述	数据表
V62/04650-01XE	TI	获取价格	Enhanced Product 1394 Integrated Phy And Link-Layer Controller 144-LQFP -40 to 85
V62/04651-01UE	TI	获取价格	Advanved LinCMOSâ¢ RAIL-TO-RAIL VERY-LOW-POW
V62/04651-02UE	TI	获取价格	Advanved LinCMOSâ¢ RAIL-TO-RAIL VERY-LOW-POW
V62/04651-03XE	TI	获取价格	Advanved LinCMOSâ¢ RAIL-TO-RAIL VERY-LOW-POW
V62/04651-04XE	TI	获取价格	Advanved LinCMOSâ¢ RAIL-TO-RAIL VERY-LOW-POW
V62/04652-01XE	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATE
V62/04652-01YE	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATE
V62/04652-02YE	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATE
V62/04653-01XE	TI	获取价格	HEX INVERTER
V62/04653-01YE	TI	获取价格	HEX INVERTER

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