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V62/04609-06XA PDF预览

V62/04609-06XA

更新时间： 2024-11-16 12:21:47
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
93页 1019K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSORS

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V62/04609-06XA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532针数：532
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.92
Is Samacsys：N其他特性：ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：23桶式移位器：NO
位大小：32边界扫描：YES
最大时钟频率：33 MHz外部数据总线宽度：64
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B532JESD-609代码：e0
长度：23 mm低功率模式：YES
湿度敏感等级：4端子数量：532
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：FBGA
封装等效代码：BGA532,26X26,32封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH峰值回流温度（摄氏度）：220
电源：1.2,3.3 V认证状态：Not Qualified
RAM（字数）：16384座面最大高度：3.3 mm
子类别：Digital Signal Processors最大供电电压：1.31 V
最小供电电压：1.19 V标称供电电压：1.25 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

V62/04609-06XA 数据手册

 浏览型号V62/04609-06XA的Datasheet PDF文件第2页浏览型号V62/04609-06XA的Datasheet PDF文件第3页浏览型号V62/04609-06XA的Datasheet PDF文件第4页浏览型号V62/04609-06XA的Datasheet PDF文件第5页浏览型号V62/04609-06XA的Datasheet PDF文件第6页浏览型号V62/04609-06XA的Datasheet PDF文件第7页 
SM320C6414-EP, SM320C6415-EP, SM320C6416-EP  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
www.ti.com  
SGUS043D–MAY 2003–REVISED SEPTEMBER 2008  
1 Introduction  
1.1 Features  
1280M-Byte Addressable External Memory  
•
Highest-Performance Fixed-Point Digital  
Signal Processors (DSPs)  
•
•
•
Enhanced Direct Memory Access (EDMA)  
Controller (64 Independent Channels)  
–
–
–
–
–
–
–
2-ns Instruction Cycle Time  
500-MHz Clock Rate  
Eight 32-Bit Instructions/Cycle  
28 Operations/Cycle  
4000 MIPS  
Fully Software Compatible With C62x™  
C6414/15/16 Devices Pin Compatible  
Host-Port Interface (HPI)  
–
User-Configurable Bus Width (32/16 Bit)  
32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface  
Conforms to PCI Specification 2.2  
(C6415/C6416)  
–
–
–
Three PCI Bus Address Registers  
Four-Wire Serial EEPROM Interface  
PCI Interrupt Request Under DSP Program  
Control  
•
VelociTI.2™ Extensions to VelociTI™  
Advanced Very Long Instruction Word (VLIW)  
TMS320C64x™ DSP Core  
–
Eight Highly Independent Functional Units  
With VelociTI.2 Extensions With Six ALUs  
and Two Multipliers  
Nonaligned Load-Store Architecture  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
–
DSP Interrupt Via PCI I/O Cycle  
•
Three Multichannel Buffered Serial Ports  
(McBSPs)  
–
–
–
–
–
Direct Interface to T1/E1, MVIP, and SCSA  
Framers  
Up to 256 Channels Each  
ST Bus Switching, AC97 Compatible  
Serial Peripheral Interface (SPI) Compatible  
(Motorola)  
–
–
–
•
Instruction Set Features  
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit Counting  
VelociTI.2 Increased Orthogonality  
•
•
Three 32-Bit General-Purpose Timers  
Universal Test and Operations Physical Layer  
(PHY) Interface for ATM (UTOPIA)  
(C6415/C6416)  
•
•
Viterbi Decoder Coprocessor (VCP) (C6416)  
–
–
UTOPIA Level-2 Slave ATM Controller  
8-Bit Transmit and Receive Operations up  
to 50 MHz per Direction  
–
Supports Over 500 7.95-Kbps Adaptive  
Multi-Rate (AMR)  
–
Programmable Code Parameters  
–
User-Defined Cell Format up to 64 Bytes  
Turbo Decoder Coprocessor (TCP) (C6416)  
•
•
16 General-Purpose I/O (GPIO) Pins  
–
Supports up to Six 2-Mbps 3GPP  
(Six Iterations)  
Flexible Phase-Locked Loop (PLL) Clock  
Generator  
IEEE Std 1149.1 (JTAG(1)) Boundary Scan  
–
Programmable Turbo Code and Decoding  
Parameters  
•
•
Compatible  
•
•
L1/L2 Memory Architecture  
532-Pin Ball Grid Array (BGA) Package (GLZ  
Suffix), 0.8-mm Ball Pitch  
–
–
–
128K-Bit (16K-Byte) L1P Program Cache  
128K-Bit (16K-Byte) L1D Data Cache  
8M-Bit (1024K-Byte) L2 Unified Mapped  
RAM/Cache  
•
•
0.13-µm/6-Level Metal Process (CMOS)  
3.3-V I/Os, 1.25-V Internal (500 MHz)  
(1) IEEE Std 1149.1-1990 Standard Test-Access Port and  
Boundary Scan Architecture  
Two External Memory Interfaces (EMIFs) for  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2008, Texas Instruments Incorporated  
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