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V62/03626-02XE PDF预览

V62/03626-02XE

更新时间: 2023-06-19 15:23:02
品牌 Logo 应用领域
德州仪器 - TI 通信时钟数据传输外围集成电路
页数 文件大小 规格书
35页 443K
描述
具有 64 字节 Fifo 的增强型产品 3.3V 双 Uart | PT | 48 | -55 to 110

V62/03626-02XE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:48
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.75地址总线宽度:3
边界扫描:NO最大时钟频率:48 MHz
通信协议:ASYNC, BIT最大数据传输速率:0.375 MBps
外部数据总线宽度:8JESD-30 代码:S-PQFP-G48
JESD-609代码:e4长度:7 mm
低功率模式:YES湿度敏感等级:3
串行 I/O 数:1端子数量:48
最高工作温度:110 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

V62/03626-02XE 数据手册

 浏览型号V62/03626-02XE的Datasheet PDF文件第2页浏览型号V62/03626-02XE的Datasheet PDF文件第3页浏览型号V62/03626-02XE的Datasheet PDF文件第4页浏览型号V62/03626-02XE的Datasheet PDF文件第5页浏览型号V62/03626-02XE的Datasheet PDF文件第6页浏览型号V62/03626-02XE的Datasheet PDF文件第7页 
TL16C752B-EP  
3.3-V DUAL UART WITH 64-BYTE FIFO  
SGLS153 – FEBRUARY 2003  
D
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
D
Optional Data Flow Resume by Xon Any  
Character  
DMA Signaling Capability for Both  
Received and Transmitted Data  
D
D
D
D
D
D
D
Extended Temperature Performance of  
–40°C to 110°C  
Supports 3.3-V Operation  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Software Selectable Baud Rate Generator  
Prescaler Provides Additional Divide By  
Four Function  
Enhanced Product Change Notification  
Qualification Pedigree  
D
Fast Access Time 2 Clock Cycle IOR/IOW  
Pulse Width  
Pin Compatible With ST16C2550 With  
Additional Enhancements  
D
Programmable Sleep Mode  
Up to 1.5-Mbps Baud Rate When Using  
Crystal (24-MHz Input Clock)  
D
Programmable Serial Interface  
Characteristics  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even, Odd, or No Parity Bit Generation  
and Detection  
Up to 3-Mbps Baud Rate When Using  
Oscillator or Clock Source (48-MHz Input  
Clock)  
– 1, 1.5, or 2 Stop Bit Generation  
D
D
D
64-Byte Transmit FIFO  
D
D
D
D
D
D
False Start Bit Detection  
64-Byte Receive FIFO With Error Flags  
Complete Status Reporting Capabilities in  
Both Normal and Sleep Mode  
Programmable and Selectable Transmit and  
Receive FIFO Trigger Levels for DMA and  
Interrupt Generation  
Line Break Generation and Detection  
Internal Test and Loopback Capabilities  
Fully Prioritized Interrupt System Controls  
D
D
Programmable Receive FIFO Trigger Levels  
for Software/Hardware Flow Control  
Software/Hardware Flow Control  
– Programmable Xon/Xoff Characters  
– Programmable Auto-RTS and Auto-CTS  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and CD)  
description  
The TL16C752B-EP is a dual-universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs,  
automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B-EP offers enhanced  
features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop  
transmission during hardware and software flow control. With the FIFO RDY register, the software gets the  
status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error  
indications, operational status, and modem interface control. System interrupts may be tailored to meet user  
requirements. An internal loopback capability allows onboard diagnostics.  
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on  
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO  
and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own  
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity  
and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors.  
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control  
operations, and has software flow control and hardware flow control capabilities.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.  
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this  
component beyond specified performance and environmental limits.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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