Datasheet > V58C2128

V58C2128

更新时间： 2024-11-24 22:24:27

品牌	Logo	应用领域
MOSEL		动态存储器双倍数据速率
页数	文件大小	规格书
59页	922K
描述
HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM

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中文翻译

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数据手册

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V58C2128 数据手册

V58C2128(804/404/164)S

HIGH PERFORMANCE

PRELIMINARY

2.5 VOLT 128 Mbit DDR SDRAM

4 BANKS X 4Mbit X 8 (804)

4 BANKS X 2Mbit X 16 (164)

4 BANKS X 8Mbit X 4 (404)

DDR333B

7.5 ns

DDR266A

7.5ns

DDR266B

10 ns

DDR200

10 ns

Clock Cycle Time (t_CK2

)

Clock Cycle Time (t_CK2.5

)

6 ns

7ns

7.5 ns

8 ns

System Frequency (f_{CK max}

)

167 MHz

143 MHz

133 MHz

125 MHz

Features

Description

The V58C2128(804/404/164)S is a four bank

■ High speed data transfer rates with system

frequency up to 166 MHz

DDR DRAM organized as 4 banks x 4Mbit x 8 (804),

4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4

(164). The V58C2128(804/404/164)S achieves high

speed data transfer rates by employing a chip archi-

tecture that prefetches multiple bits and then syn-

chronizes the output data to a system clock.

All of the control, address, circuits are synchro-

nized with the positive edge of an externally sup-

plied clock. I/O transactions are ocurring on both

edges of DQS.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at a higher rate than is possible with standard

DRAMs. A sequential and gapless data rate is pos-

sible depending on burst length, CAS latency and

speed grade of the device.

■ Data Mask for Write Control

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS Latency: 2, 2.5

■ Programmable Wrap Sequence: Sequential

or Interleave

■ Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

■ Automatic and Controlled Precharge Command

■ Power Down Mode

■ Auto Refresh and Self Refresh

■ Refresh Interval: 4096 cycles/64 ms

■ Available in 66-pin 400 mil TSOP

■ SSTL-2 Compatible I/Os

■ Double Data Rate (DDR)

■ Bidirectional Data Strobe (DQS) for input and

output data, active on both edges

■ On-Chip DLL aligns DQ and DQs transitions with

CK transitions

■ Differential clock inputs CK and CK

■ Power Supply 2.5V ± 0.2V

■ QFC options for FET control. x4 parts.

*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing

DDR 266A Supports PC2100 module with 2-3-3 timing

DDR 266B Supports PC2100 module with 2.5-3-3 timing

DDR 200 Supports PC1600 module with 2-2-2 timing

Device Usage Chart

Operating

Temperature

Range

Package Outline

CK Cycle Time (ns)

Power

Std.

Temperature

Mark

JEDEC 66 TSOP II

-6

-7

-75

-8

0°C to 70°C

•

Blank

V58C2128(804/404/164)S Rev.1.6 March 2002

12 3 4 5 6 7...59

中文翻译

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与V58C2128相关器件

型号	品牌	获取价格	描述	数据表
V58C2128164S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM
V58C2128404S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM
V58C2128804S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM
V58C2256	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM
V58C2256164S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM
V58C2256404S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM
V58C2256804S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM
V58C265164S	MOSEL	获取价格	64 Mbit DDR SDRAM 2.5 VOLT 4M X 16
V58C265404S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4
V58C265804S	MOSEL	获取价格	HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

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