Datasheet > V104

V104

更新时间： 2024-11-24 21:54:19

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
11页	206K
描述
10 BIT LVDS RECEIVER FOR VIDEO

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V104 数据手册

PRELIMINARY

V104

10 BIT LVDS RECEIVER FOR VIDEO

General Description

Features

The V104 10 Bit LVDS Receiver for Video is designed

to support video data transmission between display

engines and video processing engines for television

and projector applications. The V104 supports up to

WXGA resolutions for Plasma, Rear Projection, Front

Projection, CRT and LCD applications.

• Pin & function compatible with the THC63LVD104A

• Wide pixel clock range: 8 - 90 MHz

• Supports resolutions from 480p to WXGA

• Internal PLL does not require external loop filter

• Clock edge selection for TTL alignment selectable

• Power down mode

The V104 converts the 6 LVDS (Low Voltage

Differential Signaling) video data stream pairs to 35

CMOS/TTL data bits with a rising or falling edge clock.

The clock edge selection is performed using a

dedicated pin.

• Single 3.3V supply

• Low power consumption CMOS design

• 64-pin TQFP lead free package

In conjunction with the V103 transmitter, the V104 can

transmit 10 bits per color (R, G, B) along with 5 bits of

control and timing data (HSYNC, VSYNC, DE, CNTL1,

CNTL2) over a low EMI, low bus width connection

including connectors and standard LVDS cabling.

Block Diagram

CMOS/TTL Output

LVDS Input

RA6-RA0

RA+/-

RB6-RB0

RB+/-

RC+/-

RD+/-

Serial to

Parallel

RC6-RC0

RD6-RD0

RE6-RE0

RE+/-

PLL

CLKOUT

RCLK+/-

(8 to 90 MHz)

CMOS/TTL Input

TEST

R/F

V104 Datasheet

1/12/05

Revision 1.6

Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

12 3 4 5 6 7...11

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