Datasheet > V103YLF

V103YLF

更新时间： 2024-11-21 08:16:07

品牌	Logo	应用领域
矽成 - ICSI		驱动器接口集成电路
页数	文件大小	规格书
11页	150K
描述
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO

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V103YLF 数据手册

V103

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO

General Description

Features

The V103 LVDS display interface transmitter is

primarily designed to support pixel data transmission

between a video processing engine and a digital video

display. The data rate supports up to SXGA+

resolutions and can be used in Plasma, Rear Projector,

Front Projector, CRT and LCD display applications. It

can also be used in other high-bandwidth parallel data

applications and provides a low EMI interconnect over

a low cost, low bus width cable up to several meters in

length.

• Pin compatible with THine THC63LVD103

• Wide pixel clock range: 8 - 135 MHz

• Supports a wide range of video and graphics modes

including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,

PAL, SDTV, and HDTV up to 1080I or 720P

• Internal PLL requires no external loop filter

• Selectable rising or falling clock edge for data

alignment

• Compatible with Spread Spectrum clock source

The V103 converts 35 bits of CMOS/TTL data, clocked

on the rising or falling edge of an input clock

(selectable), into six LVDS (Low Voltage Differential

Signaling) serial data stream pairs. In video

applications the 35 bits is normally divided into 10 bits

for each R, G and B channel and 5 control bits.

• Reduced LVDS output voltage swing mode

(selectable) to minimize EMI

• CMOS/TTL data inputs can be configured for

reduced input voltage swing

• Single 3.3 V supply

When combined with the V104 LVDS display interface

receiver, the V103 + V104 combination provides a

35-bit wide, 90 MHz transport. The rate of each LVDS

channel is 630 Mbps for a 90MHz data input clock, 945

Mbps for 135MHz.

• Low power consumption CMOS design

• Power down mode

• 64-pin TQFP lead free package

Block Diagram

TA+

TA-

TA0-6

TB0-6

TB+

TB-

TC0-6

TD0-6

Parallel

to Serial

TC+

TC-

TE0-6

TD+

TD-

R/F

/PWDN

TE+

TE-

TCLK+

TCLK-

CLKIN

(8 to 135 MHz)

PLL

V103 Datasheet

11/23/06

Revision 2.0

Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

12 3 4 5 6 7...11

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