Datasheet > UT8SP2M48MZPC

UT8SP2M48MZPC

更新时间： 2024-09-17 00:50:19

品牌	Logo	应用领域
艾法斯 - AEROFLEX		静态存储器
页数	文件大小	规格书
23页	447K
描述
UT8SP2M48 96Megabit Pipelined SSRAM

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UT8SP2M48MZPC 数据手册

Standard Products

UT8SP2M48 96Megabit Pipelined SSRAM

Preliminary Datasheet

www.aeroflex.com/memories

April 2015

FEATURES

INTRODUCTION



Synchronous SRAM organized as 2Meg words x 48bit

Continuous Data Transfer (CDT) architecture eliminates

wait states between read and write operations

Supports 40MHz to 133MHz bus operations

Internally self-timed output buffer control eliminates the

need for synchronous output enable

Registered inputs and outputs for pipelined operation

Single 2.5V to 3.3V supply

Clock-to-output time

- Clk to Q = 7ns

Clock Enable (CEN) pin to enable clock and suspend

operation

Synchronous self-timed writes

Three Chip Enables (CS0, CS1, CS2) for simple depth

expansion

"ZZ" Sleep Mode option for partial power-down

"SHUTDOWN" Mode option for deep power-down

Four Word Burst Capability--linear or interleaved

Operational Environment

The UT8SP2M48 is a high performance 100,663,296-bit

synchronous static random access memory (SSRAM) device

that is organized as 2M words of 48 bits. This device is

equipped with three chip selects (CS0, CS1, and CS2), a write

enable (WE), and an output enable (OE) pin, allowing for

significant design flexibility without bus contention. The

device supports a four word burst function using (ADV_LD).



All synchronous inputs are registered on the rising edge of the

clock provided the Clock Enable (CEN) input is enabled LOW.

Operations are suspended when CEN is disabled HIGH and the

previous operation is extended. Write operation control signals

are WE and six byte write enables BWE[5:0]. All write

operations are performed by internal self-timed circuitry.



For easy bank selection, three synchronous Chip Enables

(CS0, CS1, CS2) and an asynchronous Output Enable (OE)

provide for output tri-state control. The output drivers are

synchronously tri-stated during the data portion of a write

sequence to avoid bus contention.



- Total Dose: 100 krad(Si)

- SEL Immune: ≤ 100MeV-cm /mg

-6

- SEU error rate: 1.7x10 errors/bit-day



Package options:

- 288-lead CLGA, CCGA, and CBGA

Standard Microelectronics Drawing (SMD) 5962-15213

- QMLQ and Q+ pending

36-00-01-001

Ver. 1.1.0

Aeroflex Microelectronics Solutions - HiRel

12 3 4 5 6 7...23

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