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UT7C139C45WCC

更新时间: 2024-10-14 03:22:51
品牌 Logo 应用领域
艾法斯 - AEROFLEX 内存集成电路静态存储器LORA
页数 文件大小 规格书
21页 360K
描述
4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag

UT7C139C45WCC 数据手册

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UStaTnd7arCd P1ro3du8c/ts139 4Kx8/9 Radiation-Hardened  
Dual-Port Static RAM with Busy Flag  
Data Sheet  
January 2002  
FEATURES  
INTRODUCTION  
The UT7C138 and UT7C139 are high-speed radiation-  
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.  
Arbitration schemes are included on the UT7C138/139 to  
handle situations when multiple processors access the same  
memory location. Two ports provide independent,  
asynchronous access for reads and writes to any location in  
memory. The UT7C138/139 can be utilized as a stand-alone  
32/36-Kbit dual-port static RAM or multiple devices can be  
combined in order to function as a 16/18-bit or wider master/  
slave dual-port static RAM. For applications that require  
depth expansion, the BUSY pin is open-collector allowing  
for wired OR circuit configuration. An M/S pin is provided  
for implementing 16/18-bit or wider memory applications  
without the need for separate master and slave devices or  
additional discrete logic. Application areas include  
interprocessor/multiprocessor designs, communications,  
and status buffering.  
q
q
45ns and 55ns maximum address access time  
Asynchronous operation for compatibility with industry-  
standard 4K x 8/9 dual-port static RAM  
q
CMOS compatible inputs, TTL/CMOS compatible output  
levels  
q
q
q
Three-state bidirectional data bus  
Low operating and standby current  
Radiation-hardened process and design; total dose  
irradiation testing to MIL-STD-883 Method 1019  
- Total-dose: 1.0E6 rads(Si)  
- Memory Cell LET threshold: 85 MeV-cm2/mg  
- Latchup immune (LET >100 MeV-cm2/mg)  
QML Q and QML V compliant part  
Packaging options:  
q
q
- 68-lead Flatpack  
- 68-pin PGA  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable ( OE). BUSY  
signals that the port is trying to access the same location  
currently being accessed by the other port.  
q
q
5-volt operation  
Standard Microcircuit Drawing 5962-96845  
R/W  
L
R/W  
R
CE  
OE  
L
L
CE  
OE  
R
R
A
A
11L  
10L  
A
11R  
10R  
A
I/O (7C139)  
I/O (7C139)  
8R  
8L  
COL  
SEL  
COL  
SEL  
I/O  
I/O  
COLUMN  
I/O  
COLUMN  
I/O  
7R  
7L  
I/O  
I/O  
0L  
0R  
BUSY  
A
BUSY  
R
L
A
A
9L  
0L  
ROW  
SELECT  
MEMORY  
ARRAY  
ROW  
SELECT  
9R  
A
0R  
M/S  
ARBITRATION  
Figure 1. Logic Block Diagram  

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