Datasheet > UT54LVDS032LV-UCC

UT54LVDS032LV-UCC

更新时间： 2024-10-14 03:18:51

品牌	Logo	应用领域
艾法斯 - AEROFLEX		/
页数	文件大小	规格书
11页	81K
描述
Low Voltage Quad Receiver

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Standard Products

UT54LVDS032LV Low Voltage Quad Receiver

Data Sheet

May, 2003

FEATURES

INTRODUCTION

The UT54LVDS032LV Quad Receiver is a quad CMOS

differential line receiver designed for applications requiring

ultra low power dissipation and high data rates. The device is

designed to support data rates in excess of 400.0 Mbps (200

MHz) utilizing Low Voltage Differential Signaling (LVDS)

technology.

>400.0 Mbps (200 MHz) switching rates

+340mV differential signaling

3.3 V power supply

TTL compatible outputs

Cold spare all pins

The UT54LVDS032LV accepts low voltage (340mV)

differential input signals and translates them to 3V CMOS

output levels. The receiver supports a three-state function that

may be used to multiplex outputs. The receiver also supports

OPEN, shorted and terminated (100W) input fail-safe. Receiver

output will be HIGH for all fail-safe conditions.

Ultra low power CMOS technology

4.0ns maximum propagation delay

0.35ns maximum differential skew

Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

The UT54LVDS032LV and companion quad line driver

UT54LVDS031LV provides new alternatives to high power

pseudo-ECL devices for high speed point-to-point interface

applications.

- Total-dose: 300 krad(Si) and 1Mrad(Si)

- Latchup immune (LET > 100 MeV-cm²/mg)

Packaging options:

- 16-lead flatpack (dual in-line)

All pins have Cold Spare buffers. These buffers will be high

Standard Microcircuit Drawing 5962-98652

- QML Q and Vcompliant part

impedance when V_DDis tied to V_SS

R_IN1+

R_IN1-

R_OUT1

R_IN2+

R_IN2-

R_OUT2

R_IN3+

R_IN3-

R_OUT3

R_IN4+

R_IN4-

R_OUT4

Figure 1. UT54LVDS032LV Quad Receiver Block Diagram

12 3 4 5 6 7...11

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