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UT54ACTS280 PDF预览

UT54ACTS280

更新时间: 2024-11-23 01:20:43
品牌 Logo 应用领域
艾法斯 - AEROFLEX /
页数 文件大小 规格书
10页 258K
描述
9-Bit Parity Generators/Checkers

UT54ACTS280 数据手册

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Standard Products  
UT54ACS280/UT54ACTS280  
9-Bit Parity Generators/Checkers  
Datasheet  
November 2010  
www.aeroflex.com/logic  
FEATURES  
PINOUTS  
‰ Generates either odd or even parity for nine data lines  
‰ Cascadable for n-bits parity  
14-Pin DIP  
Top View  
‰ 1.2μ CMOS  
- Latchup immune  
G
1
14  
VDD  
‰ High speed  
‰ Low power consumption  
‰ Single 5 volt supply  
‰ Available QML Q or V processes  
‰ Flexible package  
- 14-pin DIP  
H
NC  
2
3
4
5
6
7
13  
12  
11  
10  
9
F
E
D
C
B
A
I
EVEN  
ODD  
VSS  
8
- 14-lead flatpack  
‰ UT54ACS280 - SMD 5962-96582  
‰ UT54ACTS280 - SMD 5962-96583  
14-Lead Flatpack  
Top View  
DESCRIPTION  
14  
1
G
VDD  
The UT54ACS280 and the UT54ACTS280 are 9-bit parity gen-  
erators/checkers that use high-performance circuitry and fea-  
tures odd and even outputs to facilitate operation of either odd  
or even parity application. The word-length capability is easily  
expanded by cascading.  
13  
12  
11  
10  
9
2
3
4
5
6
7
H
NC  
F
E
D
C
B
A
I
EVEN  
ODD  
VSS  
The devices are characterized over full military temperature  
range of -55°C to +125°C.  
8
FUNCTION TABLE  
NUMBER OF INPUTS A THRU I  
THAT ARE HIGH  
OUTPUT  
Σ EVEN  
Σ ODD  
0,2,4,6,8  
1,3,5,7,9  
H
L
L
H
LOGIC SYMBOL  
(8)  
2k  
A
B
C
(9)  
(10)  
(11)  
(12)  
(13)  
(1)  
D
E
F
(5)  
(6)  
EVEN  
ODD  
G
H
(2)  
(4)  
I
1
Note:  
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC  
Publication 617-12.  

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