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UT54ACTS279 PDF预览

UT54ACTS279

更新时间: 2024-11-23 01:20:43
品牌 Logo 应用领域
艾法斯 - AEROFLEX /
页数 文件大小 规格书
9页 234K
描述
Quadruple S-R Latches

UT54ACTS279 数据手册

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Standard Products  
UT54ACS279/UT54ACTS279  
Quadruple S-R Latches  
Datasheet  
November 2010  
www.aeroflex.com/logic  
FEATURES  
PINOUTS  
‰ 1.2μ CMOS  
16-Pin DIP  
Top View  
- Latchup immune  
‰ High speed  
‰ Low power consumption  
‰ Single 5 volt supply  
‰ Available QML Q or V processes  
‰ Flexible package  
- 16-pin DIP  
- 16-lead flatpack  
‰ UT54ACS279- SMD 5962-96580  
‰ UT54ACTS279 - SMD 5962-96581  
1
16  
1R  
VDD  
2
3
4
5
6
7
8
15  
14  
13  
12  
11  
10  
9
1S1  
1S2  
1Q  
4S  
4R  
4Q  
3S2  
3S1  
3R  
2R  
2S  
2Q  
VSS  
3Q  
DESCRIPTION  
16-Lead Flatpack  
Top View  
The UT54ACS279 and the UT54ACTS279 contain four basic  
S-R flip-flop latches. Under conventional operation, the S-R  
inputs are normally held high. When the S input is pulsed low,  
the Q output will be set high. When R is pulsed low, the Q output  
will be reset low. If the S-R inputs are taken low simultaneously,  
the Q output is unpredictable.  
VDD  
16  
1
1R  
4S  
2
3
4
5
6
7
8
15  
14  
13  
12  
11  
10  
9
1S1  
1S2  
1Q  
4R  
4Q  
3S2  
3S1  
3R  
The devices are characterized over full military temperature  
range of -55°C to +125°C.  
2R  
2S  
2Q  
FUNCTION TABLE  
VSS  
3Q  
INPUTS  
OUTPUT  
S
H
R
H
Q
Q0  
LOGIC SYMBOL  
L
H
L
H
L
L
H
L
(1)  
1R  
R
H 1  
(2)  
(4)  
(7)  
S1  
S1  
1S1  
(3)  
1Q  
1S2  
Note:  
(5)  
1. This configuration is nonstable. It may not persist when the S and R inputs  
return to their inactive (high) level.  
R
2R  
2Q  
(6)  
S2  
R
2S  
(10)  
3R  
LOGIC DIAGRAM  
(11)  
3S1  
(12)  
3S2  
(9)  
S3  
S3  
3Q  
4Q  
(LATCHES 1 & 3)  
(LATCHES 2 & 4)  
(14)  
R
(13)  
4R  
(15)  
R
S
R
S4  
4S  
Note:  
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC  
Publication 617-12.  
S1  
S2  
Q
Q
1

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