Datasheet > UT54ACTS169

UT54ACTS169

更新时间： 2024-09-14 01:18:55

品牌	Logo	应用领域
艾法斯 - AEROFLEX		/
页数	文件大小	规格书
11页	267K
描述
4-Bit Up-Down Binary Counters

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中文翻译

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数据手册

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UT54ACTS169 数据手册

Standard Products

UT54ACS169/UT54ACTS169

4-Bit Up-Down Binary Counters

Datasheet

November 2010

www.aeroflex.com/logic

FEATURES

PINOUTS

Fully synchronous operation for counting and programming

Internal look-ahead for fast counting

Carry output for n-bit cascading

Fully independent clock circuit

16-Pin DIP

Top View

V_DD

U/D

1.2μ CMOS

RCO

Q_A

CLK

- Latchup immune

Q_B

High speed

Low power consumption

Single 5 volt supply

Available QML Q or V processes

Flexible package

- 16-pin DIP

Q_C

Q_D

ENT

LOAD

ENP

V_SS

- 16-lead flatpack

UT54ACS169 - SMD 5962-96560

UT54ACTS169 - SMD 5962-96561

16-Lead Flatpack

Top View

DESCRIPTION

U/D

The UT54ACS169 and the UT54ACTS169 are synchronous 4-

bit binary counters that feature an internal carry look-ahead for

cascading in high-speed counting applications. Synchronous

operation is provided by having all flip-flops clocked simulta-

neously so that the outputs change coincident with each other

when instructed by the count-enable inputs and internal gating.

Synchronous operation helps eliminate the output counting

spikes that are normally associated with asynchronous (ripple

clock) counters. The clock input triggers the four flip-flops on

the rising (positive-going) edge of the clock.

V_DD

CLK

RCO

Q_A

Q_B

Q_C

Q_D

ENP

V_SS

ENT

LOAD

The counters are fully programmable (i.e., the outputs may each

be preset high or low). The load input circuitry allows loading

with the carry-enable output of cascaded counters. Loading is

synchronous; applying a low level at the load input disables the

counter and causes the outputs to agree with the data inputs after

the next clock pulse.

Transitions at ENP or ENT are allowed regardless of the level

of the clock input.

The counters feature a fully independent clock circuit. Changes

at control inputs (ENP, ENT, LOAD, U/D) that modify the op-

erating mode have no effect on the contents of the counter until

clocking occurs. The function of the counter (whether enabled,

disabled, loading, or counting) will be dictated solely by the

conditions meeting the stable setup and hold times.

The carry look-ahead circuitry provides for cascaded counters

for n-bit synchronous application without additional gating. In-

strumental in accomplishing this function are two count-enable

inputs and a carry output. Assert both count enable inputs (ENP

and ENT) to count. The direction of the count is determined by

the level of the U/D input. When U/D is high, the counter counts

up; when low, it counts down. Input ENT is fed forward to

enable the carry output. The ripple carry output

The devices are characterized over full military temperature

range of -55°C to +125°C.

RCO enables a low-level pulse while the count is zero (all inputs

low) counting down or maximum (15) counting up. The low-

level overflow carry pulse can be used to enable successive cas-

caded stages.

12 3 4 5 6 7...11

中文翻译

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与UT54ACTS169相关器件

型号	品牌	获取价格	描述	数据表
UT54ACTS169-PCA	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PCC	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PCX	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQAH	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQAR	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQCH	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQCR	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQXH	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQXR	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PVAH	ETC	获取价格	Synchronous Up/Down Counter

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