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UT54ACTS164E PDF预览

UT54ACTS164E

更新时间: 2024-09-14 01:18:55
品牌 Logo 应用领域
艾法斯 - AEROFLEX /
页数 文件大小 规格书
9页 158K
描述
8-Bit Shift Registers

UT54ACTS164E 数据手册

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UT54ACS164E/UT54ACTS164E  
8-Bit Shift Registers  
October, 2008  
www.aeroflex.com/Logic  
FEATURES  
FUNCTION TABLE  
AND-gated (enable/disable) serial inputs  
Fully buffered clock and serial inputs  
Direct clear  
INPUTS  
OUTPUTS  
QB ... QH  
CLR  
CLK  
A
B
QA  
L
X
L
X
X
X
X
L
L
L
• 0.6μm CRH CMOS Process  
- Latchup immune  
H
QA0  
QB0  
QH0  
High speed  
H
H
H
H
L
H
X
L
H
L
L
QAn  
QAn  
QAn  
QGn  
QGn  
QGn  
Low power consumption  
Wide operating power supply from 3.0V to 5.5V  
Available QML Q or V processes  
14-lead flatpack  
X
Notes:  
DESCRIPTION  
1. QA0, QB0, QH0 = the level of QA, QB or QH, respectively, before the indicated  
steady-state input conditions were established.  
The UT54ACS164E and the UT54ACTS164E are 8-bit shift  
registers which feature AND-gated serial inputs and an asyn-  
chronous clear. The gated serial inputs (A and B) permit com-  
plete control over incoming data. A low at either input inhibits  
entry of new data and resets the first flip-flop to the low level  
at the next clock pulse. A high-level at both serial inputs sets  
the first flip-flop to the high level at the next clock pulse. Data  
at the serial inputs may be changed while the clock is high or  
low, providing the minimum setup time requirements are met.  
Clocking occurs on the low-to-high-level transition of the clock  
input.  
2. QAn and QGn = the level of QA or QG before the most recent transition of  
the clock; indicates a one-bit shift.  
ThedevicesarecharacterizedoverfullHiReltemperaturerange  
LOGIC SYMBOL  
of -55°C to +125°C.  
SRG8  
(9)  
CLR  
CLK  
R
(8)  
C1/  
PINOUT  
(1)  
(2)  
A
B
&
(3)  
(4)  
14-Lead Flatpack  
Top View  
1D  
QA  
QB  
(5)  
(6)  
QC  
QD  
QE  
QF  
QG  
QH  
1
14  
A
VDD  
2
3
4
5
6
7
13  
12  
11  
10  
9
B
QA  
QB  
QC  
QD  
VSS  
QH  
(10)  
(11)  
(12)  
(13)  
QG  
QF  
QE  
CLR  
CLK  
8
Note:  
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
1

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