Datasheet > UT54ACTS164

UT54ACTS164

更新时间： 2024-09-14 01:18:55

品牌	Logo	应用领域
艾法斯 - AEROFLEX		/
页数	文件大小	规格书
10页	246K
描述
8-Bit Shift Registers

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中文翻译

获取价格

数据手册

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UT54ACTS164 数据手册

Standard Products

UT54ACS164/UT54ACTS164

8-Bit Shift Registers

Datasheet

November 2010

www.aeroflex.com/logic

FEATURES

PINOUTS

AND-gated (enable/disable) serial inputs

Fully buffered clock and serial inputs

Direct clear

14-Pin DIP

Top View

1.2μ CMOS

V_DD

- Latchup immune

Q_H

Q_A

Q_B

Q_C

Q_D

V_SS

High speed

Low power consumption

Single 5 volt supply

Available QML Q or V processes

Flexible package

- 14-pin DIP

Q_G

Q_F

Q_E

CLR

CLK

- 14-lead flatpack

UT54ACS164 - SMD 5962-96556

UT54ACTS164 - SMD 5962-96557

14-Lead Flatpack

Top View

DESCRIPTION

V_DD

The UT54ACS164 and the UT54ACTS164 are 8-bit shift reg-

isters which feature AND-gated serial inputs and an asynchro-

nous clear. The gated serial inputs (A and B) permit complete

control over incoming data. A low at either input inhibits entry

of new data and resets the first flip-flop to the low level at the

next clock pulse. A high-level at both serial inputs sets the first

flip-flop to the high level at the next clock pulse. Data at the

serial inputs may be changed while the clock is high or low,

providingtheminimumsetuptimerequirementsaremet. Clock-

ing occurs on the low-to-high-level transition of the clock input.

Q_A

Q_B

Q_C

Q_D

V_SS

Q_H

Q_G

Q_F

Q_E

CLR

CLK

LOGIC SYMBOL

The devices are characterized over full military temperature

range of -55°C to +125°C.

SRG8

(9)

CLR

(8)

FUNCTION TABLE

CLK

C1/

INPUTS

CLK

OUTPUTS

Q_{B ...}Q_H

(1)

(3)

(4)

(2)

Q_A

CLR

Q_A

Q_B

(5)

(6)

Q_C

Q_D

Q_E

Q_F

Q_G

Q_H

Q_A0

Q_B0

Q_H0

(10)

(11)

(12)

(13)

↑

Q_An

Q_Gn

Notes:

Note:

1. Q_A0, Q_B0, Q_H0= the level of Q_A, Q_Bor Q_H, respectively, before the indicated

1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

steady-state input conditions were established.

2. Q_Anand Q_Gn= the level of Q_Aor Q_Gbefore the most recent ↑ transition of

the clock; indicates a one-bit shift.

12 3 4 5 6 7...10

中文翻译

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UT54ACTS169-PCX	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQAH	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQAR	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQCH	ETC	获取价格	Synchronous Up/Down Counter
UT54ACTS169-PQCR	ETC	获取价格	Synchronous Up/Down Counter