Datasheet > UT54ACTS163

UT54ACTS163

更新时间： 2024-02-16 11:14:37

品牌	Logo	应用领域
艾法斯 - AEROFLEX		/
页数	文件大小	规格书
10页	255K
描述
4-Bit Synchronous Counters

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中文翻译

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数据手册

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UT54ACTS163 数据手册

Standard Products

UT54ACS163/UT54ACTS163

4-Bit Synchronous Counters

Datasheet

November 2010

www.aeroflex.com/logic

FEATURES

PINOUTS

Internal look-ahead for fast counting

Carry output for n-bit cascading

Synchronous counting

16-Pin DIP

Top View

V_DD

CLR

Synchronously programmable

RCO

Q_A

CLK

1.2μ CMOS

- Latchup immune

Q_B

High speed

Low power consumption

Single 5 volt supply

Q_C

Q_D

ENP

V_SS

ENT

LOAD

Available QML Q or V processes

Flexible package

- 16-pin DIP

- 16-lead flatpack

UT54ACS163 - SMD 5962-96554

UT54ACTS163 - SMD 5962-96555

16-Lead Flatpack

Top View

DESCRIPTION

V_DD

CLR

The UT54ACS163 and the UT54ACTS163 are synchronous

presettable 4-bit binary counters that feature internal carry look-

ahead logic for high-speed counting designs. Synchronous op-

eration occurs by having all flip-flops clocked simultaneously

so that the outputs change coincident with each other when in-

structed by the count-enable inputs and internal gating. A buff-

ered clock input triggers the four flip-flops on the rising (posi-

tive-going) edge of the clock input waveform.

RCO

Q_A

CLK

Q_B

Q_C

Q_D

ENP

V_SS

ENT

LOAD

The counters are fully programmable (i.e., they may be preset

to any number between 0 and 15). Presetting is synchronous;

applying a low level at the load input disables the counter and

causes the outputs to agree with the load data after the next clock

pulse.

LOGIC SYMBOL

CTRDIV 16

5CT=0

(1)

CLR

(9)

LOAD

(15)

RCO

3CT = 15

(10)

The clear function is synchronous and a low level at the clear

input sets all four of the flip-flop outputs low after the next clock

pulse. This synchronous clear allows the count length to be mod-

ified by decoding the Q outputs for the maximum count desired.

ENT

(7)

ENP

(2)

CLK

C5/2,3,4+

(3)

(14)

(13)

(12)

(11)

(1)

1,5D

Q_A

Q_B

Q_C

Q_D

The counters feature a fully independent clock circuit. Changes

at control inputs (ENP, ENT, or LOAD) that modify the operat-

ing mode have no effect on the contents of the counter until

clocking occurs. The function of the counter (whether enabled,

disabled, loading, or counting) will be dictated solely by the

conditions meeting the stable setup and hold times.

(4)

(2)

(4)

(8)

(5)

(6)

Note:

1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-

cation 617-12.

The devices are characterized over full military temperature

range of -55°C to +125°C.

12 3 4 5 6 7...10

中文翻译

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与UT54ACTS163相关器件

型号	品牌	获取价格	描述	数据表
UT54ACTS163-PCA	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PCC	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PCX	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PQAH	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PQAR	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PQCH	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PQCR	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PQXH	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PQXR	ETC	获取价格	Synchronous Up Counter
UT54ACTS163-PVAH	ETC	获取价格	Synchronous Up Counter

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