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UT54ACTQ16374UCX PDF预览

UT54ACTQ16374UCX

更新时间: 2024-10-15 00:58:39
品牌 Logo 应用领域
艾法斯 - AEROFLEX 逻辑集成电路触发器
页数 文件大小 规格书
14页 144K
描述
RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs

UT54ACTQ16374UCX 数据手册

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Standard Products  
UT54ACTQ16374  
RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and  
Three-State Outputs  
Datasheet  
May 16, 2012  
www.aeroflex.com/radhard  
FEATURES  
PIN DESCRIPTION  
16 non-inverting D flip-flops with three-state outputs  
Guaranteed simultaneously switching noise level and dy-  
namic threshold performance  
Buffered positive edge-triggered clock  
Separate control logic for each byte  
Pin Names  
Description  
OEn  
CPn  
Output Enable Input (Active Low)  
Clock Pulse Input  
Inputs  
I0-I15  
O0-O15  
Guaranteed pin-to-pin output skew  
Outputs  
TM  
0.6m Commercial RadHard CMOS  
- Total dose: 100K rad(Si)  
- Single Event Latchup immune  
LOGIC SYMBOL  
2
- SEU Onset LET >95 MeV -cm /mg  
High speed, low power consumption  
Output source/sink 24mA  
Standard Microcircuit Drawing 5962-06245  
- QML compliant part  
OE1  
CP1  
(1)  
EN2  
(48)  
C1  
EN4  
OE2 (24)  
CP2 (25)  
C3  
Package:  
(47)  
(2)  
- 48-lead flatpack, 25 mil pitch (.390 x .640)  
O0  
I0  
2
1D  
(46)  
I1  
(3)  
(5)  
(6)  
(8)  
O1  
O2  
O3  
O4  
DESCRIPTION  
(44)  
I2  
(43)  
I3  
The 16-bit wide UT54ACTQ16374 D flip-flop is built using  
TM  
(41)  
I4  
Aeroflex’s Commercial RadHard epitaxial CMOS technolo-  
(40)  
I5  
(9)  
(11)  
(12)  
(13)  
(14)  
(16)  
(17)  
gy and is ideal for space applications. This high-speed, low pow-  
er UT54ACTQ16374 D flip-flop is designed for bus oriented  
applications. A buffered clock (CP) and Output Enable (OE) are  
common to each byte and can be shorted together for full 16-bit  
operation. The UT54ACTQ16374 are particularly suitable for  
implementing buffer registers, I/O ports, bidirectional bus driv-  
ers and working registers. Each flip-flop will store the state of  
their indivdual D inputs (In) that meet the setup and hold re-  
quirements on the low-to-high clock (CPn) transition. With the  
Output Enable (OEn) low, the contents of the flip-flops are avail-  
able at the output. When OEn is high, the outputs go to high  
impedancestate. OperationofOEninputdoesnotaffectthestate  
of the D flip-flops.  
O5  
O6  
(38)  
I6  
(37)  
I7  
O7  
(36)  
I8  
3D  
4
O8  
O9  
(35)  
I9  
(33)  
I10  
O10  
O11  
O12  
(32)  
I11  
(19)  
(20)  
(22)  
(23)  
(30)  
I12  
(29)  
I13  
O13  
O14  
(27)  
I14  
(26)  
I15  
O15  

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