Standard Products
UT54ACS273/UT54ACTS273
Octal D-Flip-Flops with Clear
Datasheet
December 16, 2011
www.aeroflex.com/logic
FEATURES
PINOUTS
20-Pin DIP
Top View
Contains eight flip-flops with single-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
- Buffer/storage registers, shift registers, and pattern
generators
CMOS
V
20
19
18
17
16
CLR
1Q
1D
1
2
3
4
5
DD
8Q
8D
7D
7Q
2D
2Q
- Latchup immune
6
7
6Q
6D
3Q
3D
15
14
High speed
Low power consumption
Single 5 volt supply
8
4D
4Q
13
12
11
5D
9
5Q
Available QML Q or V processes
Flexible package
10
V
CLK
SS
- 20-pin DIP
- 20-lead flatpack
UT54ACS273 - SMD 5962-96578
UT54ACTS273 - SMD 5962-96579
20-Lead Flatpack
Top View
CLR
1
20
V
DD
DESCRIPTION
1Q
1D
2D
2Q
3Q
3D
4D
4Q
2
19
18
17
16
15
14
13
12
11
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
The UT54ACS273 and the UT54ACTS273 are positive-edge-
triggered D-type flip-flops with a direct clear input.
3
4
Information at the D inputs meeting the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse. When the clock input is at either the high or low
level, the D input signal has no effect at the output.
5
6
7
8
9
The devices are characterized over full military temperature
range of -55C to +125C.
10
V
SS
FUNCTION TABLE
LOGIC SYMBOL
INPUTS
CLK
OUTPUTS
CLR
D
x
Q
x
(1)
CLR
L
X
X
L
R
(11)
CLK
C1
H
H
L
H
(2)
(5)
(6)
(3)
1D
1Q
2Q
3Q
H
H
L
1D
(4)
2D
X
No change
(7)
3D
L
(9)
(12)
(15)
(16)
(19)
(8)
4Q
5Q
6Q
7Q
8Q
4D
(13)
5D
(14)
6D
(17)
7D
(18)
8D
1
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.