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UT32BS1X833ZPC PDF预览

UT32BS1X833ZPC

更新时间: 2024-01-03 20:53:52
品牌 Logo 应用领域
艾法斯 - AEROFLEX /
页数 文件大小 规格书
17页 997K
描述
UT32BS1X833 Matrix-DTM 32-Channel 1 - 8 Bus Switch

UT32BS1X833ZPC 数据手册

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UStaTnd3ard2PBroSdu1ctXs 833 Matrix-D™ 32-Channel 1:8 Bus Switch  
Advanced Data Sheet  
November 12, 2014  
www.aeroflex.com/busswitch  
FEATURES  
INTRODUCTION  
Interfaces to standard processor memory busses  
Single-chip interface that provides memory paging to  
industry-standard SDRAMS  
Eliminates need for additional logic or FPGA  
I/O channels functional to 3.3V  
The UT32BS1X833 Matrix-D™ is a 32-Channel, 1:8 Bus  
Switch, that provides bus isolation for up to eight banks of 32 I/  
O connections. By providing bus isolation, the UT32BS1X833  
can significantly reduce the amount of load capacitance seen by  
ahostprocessorandmemorydevices.Theenabletooutputdelay  
time is only 4.1ns (typical). The reduction in both load  
capacitance and delay time significantly increase speed and  
performance compared with a discrete logic or FPGA memory  
interface solution.  
R
5 Ohms typical  
ON  
Flat R characteristics over channel voltage  
ON  
Propagation delay 300ps through switch  
Transmission gate technology allows for true bi-directional  
operation  
Internal pull-up resistors on the first 8 outputs of each bank  
toensurememorydevicesremaininoffstatewhenchannels  
de-selected  
Busholdersmaintainoutputstatesonallotheroutputswhen  
channels de-selected  
Logic power 1mW/MHz  
Temperature range -55°C to 125°C  
Operational environment:  
The UT32BS1X833 operates from a single 3.3V supply. The  
bus channels can pass any voltage between V and V  
,
SS  
DD  
allowing the switching of signals using other standards, such as  
LVCMOS 1.8V. The input and output banks connect via analog  
channels that have an R that is nominally 5 Ohms over the  
ON  
entire input voltage range. The flat R eliminates the need to  
ON  
add external series resistors for source impedance termination.  
The UT32BS1X833 has a “broadcast mode” that is enabled by  
driving both SDCS[1] and SDCS[0] low. In this mode, all banks  
are active, which facilitates SDRAM refresh and initialization  
cycles.  
- Intrinsic total-dose: up to 300 krad(Si)  
2
- SEL Immune <100 MeV-cm /mg  
Packaging options:  
Each UT32BS1X833 can interface up to eight of the Aeroflex  
2.5Gb or 3.0Gb SDRAM MCM devices with any Aeroflex  
LEON processor without the need for additional logic.  
- 400-pin Ceramic Land Grid, Column Grid and Ball  
Grid Array packages; 1mm pitch  
Standard Microcircuit Drawing 5962-TBD  
- QML Q and V (pending)  
APPLICATIONS  
- Microprocessor interfaces that require large amounts of  
SDRAM memory  
- High-speed applications or systems with large bus  
capacitance  
- Cost-sensitive applications that require bus isolation  
without an expensive FPGA  
- Large SDRAM paging architecture  
1
36-00-03-002  
Aeroflex Microelectronics Solutions - HiRel  

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