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UPD784224YGK-XXX-BE9 PDF预览

UPD784224YGK-XXX-BE9

更新时间： 2024-10-14 15:56:11
品牌 Logo 应用领域
日电电子 - NEC 时钟微控制器外围集成电路
页数 文件大小 规格书
92页 673K
描述
Microcontroller, 16-Bit, MROM, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80

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UPD784224YGK-XXX-BE9 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：80
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.83具有ADC：YES
地址总线宽度：20位大小：16
最大时钟频率：12.5 MHzDAC 通道：YES
DMA 通道：NO外部数据总线宽度：8
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
长度：12 mmI/O 线路数量：67
端子数量：80PWM 通道：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
ROM可编程性：MROM座面最大高度：1.27 mm
最大供电电压：5.5 V最小供电电压：1.8 V
表面贴装：YES技术：MOS
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

UPD784224YGK-XXX-BE9 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD784224, 784225, 784224Y, 784225Y  
16/8-BIT SINGLE-CHIP MICROCONTROLLERS  
The µPD784224 and 784225 are products of the µPD784225 Subseries in the 78K/IV Series. Besides a high-  
speed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A  
converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral  
hardware.  
The µPD784224Y and 784225Y are based on the µPD784225 Subseries with the addition of a multimaster-  
supporting I2C bus interface.  
Flash memory versions, the µPD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM  
version with flash memory, and various development tools are also available.  
The functions are explained in detail in the following user’s manuals. Be sure to read this manual when  
designing your system.  
µPD784225, 784225Y Subseries User’s Manual - Hardware : U12697E  
78K/IV Series User’s Manual - Instruction  
: U10905E  
FEATURES  
• I2C bus  
• Standby function  
HALT/STOP/IDLE mode  
• ROM correction  
In power-saving mode: HALT/IDLE mode (with  
subsystem clock)  
• Inherits peripheral functions of µPD780058Y  
Subseries  
• Clock division function  
• Minimum instruction execution time  
160 ns (main system clock fXX = 12.5 MHz)  
61 µs (subsystem clock fXT = 32.768 kHz)  
• I/O port: 67 pins  
• Watch timer: 1 channel  
• Watchdog timer: 1 channel  
• Clock output function  
fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT  
selectable  
• Timer/counter: 16-bit timer/counter × 1 unit  
8-bit timer/counter × 4 units  
• Buzzer output function  
• Serial interface: 3 channels  
UART/IOE (3-wire serial I/O): 2 channels  
CSI (3-wire serial I/O, multi-master supporting I2C  
busNote): 1 channel  
fXX/210, fXX/211, fXX/212, fXX/213 selectable  
• A/D converter: 8-bit resolution × 8 channels  
• D/A converter: 8-bit resolution × 2 channels  
• Supply voltage: VDD = 1.8 to 5.5 V  
Note µPD784225Y Subseries only  
APPLICATION FIELD  
Car audio, portable audio, telephones, etc.  
Unless contextually excluded, references in this document to µPD784225 mean µPD784224, 784225, 784224Y,  
and 784225Y.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Document No. U12376EJ1V0DS00 (1st edition)  
Date Published May 2000 J CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
1997, 2000  
©
1234567...92

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