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UPD720160AGC-XXX-8EA PDF预览

UPD720160AGC-XXX-8EA

更新时间: 2024-11-19 23:40:27
品牌 Logo 应用领域
其他 - ETC 总线控制器外围集成电路ISM频段时钟
页数 文件大小 规格书
32页 240K
描述
BUS CONTROLLER

UPD720160AGC-XXX-8EA 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD720110A,720160A  
USB2.0 HUB CONTROLLER  
The µPD720110A, 720160A are USB 2.0 hub devices that comply with the Universal Serial Bus (USB)  
Specification Revision 2.0 and work up to 480 Mbps. USB2.0 compliant transceivers are integrated for all upstream  
and downstream ports. The µPD720110A, 720160A work backward compatible either when any one of downstream  
ports are connected to an USB 1.1 compliant device, or when the upstream port is connected to a USB 1.1  
compliant host.  
The µPD720110A includes the default descriptors. The µPD720160A is the same silicon as the µPD720110A,  
and it has the Mask ROM option that supports customized string descriptors. By putting descriptors into ROM, the  
user's information can be implemented in the chip.  
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.  
µPD720110A, 720160A User’s Manual: S15738E  
FEATURES  
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)  
High-speed or full-speed packet protocol sequencer for Endpoint 0/1  
4 (Max.) downstream facing ports  
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)  
transaction.  
Supports split transaction to handle full-speed and low-speed transaction at downstream facing ports when Hub  
controller is working at high-speed mode.  
One Transaction Translator per Hub and supports 4 concurrent non-periodic transactions  
Supports self-powered mode only  
Supports Over-current detection and Individual power control (Gang power control supports only when external  
Serial ROM using)  
Supports configurable vendor ID and product ID with external Serial ROM  
Supports “non-removable” attribution on individual port  
System clock is generated by 30 MHz X’tal, 30 MHz clock input, or 48 MHz clock input.  
HS detection indicator output  
3.3 V power supply  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S15737EJ3V0DS00 (3rd edition)  
Date Published March 2002 NS CP (K)  
Printed in Japan  
The mark shows major revised points.  
2001  
©

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