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UPD720100AGM-8EY

更新时间： 2024-11-19 12:16:59
品牌 Logo 应用领域
日电电子 - NEC 总线控制器微控制器和处理器外围集成电路数据传输PC时钟
页数 文件大小 规格书
32页 303K
描述
MOS INTEGRATED CIRCUIT

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UPD720100AGM-8EY 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP,
针数：160Reach Compliance Code：compliant
ECCN代码：3A001.A.3HTS代码：8542.31.00.01
风险等级：5.49Is Samacsys：N
地址总线宽度：32总线兼容性：PCI
最大时钟频率：48 MHz最大数据传输速率：60 MBps
外部数据总线宽度：32JESD-30 代码：S-PQFP-G160
JESD-609代码：e0长度：24 mm
端子数量：160最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：24 mm
uPs/uCs/外围集成电路类型：BUS CONTROLLER, UNIVERSAL SERIAL BUSBase Number Matches：1

UPD720100AGM-8EY 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD720100A  
USB2.0 HOST CONTROLLER  
The µPD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller  
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for  
high-speed signaling and works up to 480 Mbps. The µPD720100A is integrated three host controller cores with PCI  
interface and USB2.0 transceivers into a single chip.  
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.  
µPD720100A User’s Manual: S15534E  
FEATURES  
•
•
•
•
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)  
Compliant with Open Host Controller Interface Specification for USB Rev 1.0a  
Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95  
PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI  
host controller core for high-speed signaling.  
•
•
Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core  
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)  
transaction.  
•
•
•
•
•
•
•
•
Configurable number of downstream facing ports (2 to 5)  
32-bit 33 MHz host interface compliant to PCI Specification release 2.2.  
Supports PCI Mobile Design Guide Revision 1.1.  
Supports PCI-Bus Power Management Interface Specification release 1.1.  
PCI Bus bus-master access  
System clock is generated by 30 MHz X’tal or 48 MHz clock input.  
Operational registers direct-mapped to PCI memory space  
Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard  
implementation.  
•
3.3 V power supply, PCI signal pins have 5 V tolerant circuit.  
ORDERING INFORMATION  
Part Number  
Package  
µPD720100AGM-8ED  
µPD720100AGM-8EY  
µPD720100AS1-2C  
160-pin plastic LQFP (Fine pitch) (24 × 24)  
160-pin plastic LQFP (Fine pitch) (24 × 24)  
176-pin plastic FBGA (15 × 15)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S15535EJ2V0DS00 (2nd edition)  
Date Published October 2002 NS CP (K)  
Printed in Japan  
The mark shows major revised points.  
2001  
©
1234567...32

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