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UPD70F3201GC-8EU PDF预览

UPD70F3201GC-8EU

更新时间: 2024-01-03 07:50:08
品牌 Logo 应用领域
日电电子 - NEC 微控制器
页数 文件大小 规格书
98页 774K
描述
32-BIT SINGLE-CHIP MICROCONTROLLERS

UPD70F3201GC-8EU 技术参数

生命周期:ObsoleteReach Compliance Code:compliant
风险等级:5.84位大小:32
CPU系列:V850JESD-30 代码:S-PQFP-G100
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:2.5 V认证状态:Not Qualified
RAM(字节):16384ROM(单词):65536
ROM可编程性:FLASH速度:17 MHz
子类别:Microcontrollers标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

UPD70F3201GC-8EU 数据手册

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PRELIMINARY PRODUCT INFORMATION  
MOS INTEGRATED CIRCUIT  
µ
PD703201, 703201Y, 703204, 703204Y,  
70F3201, 70F3201Y, 70F3204, 70F3204Y  
V850ES/SA2TM, V850ES/SA3TM  
32-BIT SINGLE-CHIP MICROCONTROLLERS  
DESCRIPTION  
The µPD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2), µPD703204, 703204Y, 70F3204, and  
70F3204Y (V850ES/SA3) are products in the V850 FamilyTM of 32-bit single-chip microcontrollers, and include  
peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a  
DMA controller.  
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2  
and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions  
executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control  
system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio  
applications.  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
V850ES/SA2, V850ES/SA3 User’s Manual Hardware:  
V850ES User’s Manual Architecture:  
To be prepared  
To be prepared  
FEATURES  
{ Number of instructions: 83  
{ Interrupts and exceptions  
{ Minimum instruction execution time:  
59 ns (@ 17 MHz operation with main system clock (fXX))  
74 ns (@ 13.5 MHz operation with main system clock (fXX))  
{ General-purpose registers: 32 bits × 32 registers  
{ Instruction set:  
Non-maskable interrupts: 2 sources  
Maskable interrupts:  
38 sources (µPD703201, 70F3201)  
39 sources (µPD703201Y, 70F3201Y)  
39 sources (µPD703204, 70F3204)  
40 sources (µPD703204Y, 70F3204Y)  
Software exceptions: 32 sources  
Exception trap: 1 source  
Signed multiplication, saturation operations, 32-bit  
shift instructions, bit manipulation instructions,  
load/store instructions  
{ Memory space:  
{ I/O lines Total: 82 (V850ES/SA2)  
102 (V850ES/SA3)  
64 MB linear address space  
Memory block division function:  
{ Timer/counters  
2 MB, 2 MB, 4 MB, 8 MB = Total four blocks  
{ External bus interface: 16-bit data bus  
Address bus: Separate output enabled  
{ Internal memory  
16-bit timer: 2 channels  
8-bit timer: 4 channels  
{ Real-time counter (for watch): 1 channel  
{ Watchdog timer: 1 channel  
Mask ROM:  
256 KB (µPD703201, 703201Y,  
703204, 703204Y)  
Flash memory: 256 KB (µPD70F3201, 70F3201Y,  
70F3204, 70F3204Y)  
RAM: 16 KB  
The information contained in this document is being issued in advance of the production cycle for the  
device. The parameters for the device may change before final production or NEC Corporation, at its own  
discretion, may withdraw the device prior to its production.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U15436EJ1V0PM00 (1st edition)  
Date Published June 2001 N CP(K)  
Printed in Japan  
2001  
©

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