New generation Gate Array with large scale embedded SRAM
CMOS-12M
CMOS-12M is NEC Electronics’ new generation Gate Array with embedded high-density SRAMs and analog
PLLs. This product offers low price, quick design turnaroundtime and quick manufacturing turnaroundtime.
CMOS-12M enables the integration of large size SRAM modules and is capable of supporting up to 2.6 Mb of
embedded SRAM.
Characteristics
Many master slice options
Ten master slices (μ PD66201 to 66210) are available to support different types of design configurations. The
largest embedded SRAM product supports 1.6 M gates and 2.6 Mb of SRAM.
0.15 μ m CMOS process technology
This technology offers 60% performance improvement over 0.25 μ m Gate Array and can operate at 200
MHz (local: 333 MHz) system frequency.
High-density SRAM
The dual-port SRAM (1R/W + 1R/W) that operates at 200 MHz is specially designed.
This dual-port SRAM can be freely reconfigured as a single-port SRAM or into a bit × word configuration that
a customer may require.
This dual-port SRAM realizes approximately 10 times the density of a conventional 0.25 μ m gate array.
The capacity of the dual-port SRAM (1R/W + 1R/W) mounted in the μ PD66201 to 66205 is 16 Kb (max.) per
unit, and that of the μ PD66206 to 66210 is 18 Kb (max.) per unit.
Embedded analog PLL and DLL
Two types of analog PLL blocks are diffused in each master slice: SSCG (Spread Spectrum Clock
Generation) and Phase Shift. Moreover, DLL (Slave DLL) blocks, which enable the DDR memory interface,
will also be diffused in μ PD66206 to 66210.
Power line architecture
Multi-voltage support
VDDQ3
CMOS-12M supports a 1.5 V core voltage and a 3.3 V
interface voltage. An optional 2.5 V, 1.8 V, or 1.5 V
interface voltage to support various high-speed interface
standards can also be added. This optional interface
voltage can be assigned to any side of the chip.
Three types of power lines are assigned on the chip--one
for the core power line, one for the standard 3.3 V
interface power line, and one for the optional high-speed
interface power line (VDDQ).
APLL
VDDQ2
(SSCG)
VDDQ4
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
Sea of Gates
VDD33
VDD
APLL
(Phase
shift)
APLL
(Phase
shift)
Applications
Designs suitable for CMOS-12M are those that require:
- Large-size memory blocks
- High performance
- Low power consumption
- Small area
VDDQ1
Power line for standard interface buffers (3.3 V)
Power line for high-speed interface buffers (2.5 V /1.8 V /1.5 V)
Power line for the core (1.5 V)
VDD33:
VDDQ1-VDDQ4:
VDD:
- Reduction in cost
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. A17424EJ3V0PF00 (3rd edition)
Date Published January 2006 CP(K)
©
NEC Electronics Corporation 2005