ISSP1
Standard Family
ISSPSeries
Features (continued)
Description
The ISSP1 Standard family represents the first generation of NEC Electronics’ Instant
Silicon Solutions Platform™ (ISSP™)—products that have established the reputation of
ISSP as the industry’s premier structured ASIC family for accelerated ROI. Based on NEC
Electronics’ 150 nm (UX4) CMOS process, the ISSP1-STD family implements complex
ASIC designs with global clock frequencies as high as 250 MHz. ISSP delivers close to
cell-based ASIC performance levels and a complex multi-gate (CMG)-based logic fabric
that delivers high performance and low power. The ISSP prefabricated architecture
incorporates clock domains, design-for-test (DFT) circuitry, global routes, and other
resources into the fabric of the chip. This architecture simplifies the design flow and
enables exceptionally fast manufacturing turnaround. Further improving the ROI equa-
tion, NRE costs are as much as an order of magnitude lower than those of cell-based
ASICs. ISSP1-STD is the ideal solution for low- to mid-volume production levels.
Design Performance,
Turnaround Time
Advantage
To improve performance and shorten turnaround, the ISSP prefabricated structure
includes multiple SRAM blocks and high-speed analog phase-locked loops (APLLs)
with phase-shift capability for versatile clock generation. An embedded clock structure
enables design with predictable and minimized clock skew. Since several types of DFT
circuits are embedded in every ISSP1-STD master, there is no danger of functional or
timing resimulations after test insertion. An embedded power mesh means fewer power
integrity issues. Additionally, the architecture provides a large array of complex multi-
gates for implementing custom logic. The use of complex logic elements makes it
possible to optimize transistor sizes for different functions, thus improving custom logic
performance.
With many elements that are traditionally executed in the ASIC design flow embedded
into its architecture, ISSP has a greatly simplified design flow that minimizes design
iterations. The entire base master architecture has been preverified to eliminate signal
integrity issues that can result in development delays. As a result, ISSP1-STD devices
enable a much shorter design cycle than cell-based ASICs. Manufacturing time is
extremely short because only two metal layers must be added to customize an ISSP1-
STD master with a custom logic design.
Block Diagram
Low-Risk Advantage
Advantages
By providing a fast-turn solution with low NRE costs, ISSP1-STD makes it practical to
develop high-performance ASICs for modest production volumes. If volumes need to
increase, the design can migrate easily to an NEC Electronics cell-based product using
the same process technology and based on the same IP and design flow.
• Low overall development costs, engineering resources and mask NRE expenses for
quick ROI
• Built-in DFT circuits, clocks, SRAM, signal integrity assurance and other features that
simplify the design process and boost performance
• Logic structure with optimized transistor sizes to improve design performance
• Mid-volume production capabilities with extremely fast turnaround times
• Predictable flow for layout and turnaround times
• Ability to leverage cell-based IP for easy migration to cell-based ASICs
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