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UPD46365184BF1-E33-EQ1-A PDF预览

UPD46365184BF1-E33-EQ1-A

更新时间: 2024-11-14 11:00:31
品牌 Logo 应用领域
瑞萨 - RENESAS 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
39页 592K
描述
QDRII/DDRII/ QDRII+/DDRII+ SRAM, LBGA, /Tray

UPD46365184BF1-E33-EQ1-A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LBGA
包装说明:BGA-165针数:165
Reach Compliance Code:unknownFactory Lead Time:1 week
风险等级:5.79最长访问时间:0.45 ns
JESD-30 代码:R-PBGA-B165长度:15 mm
内存密度:37748736 bit内存集成电路类型:QDR SRAM
内存宽度:18功能数量:1
端子数量:165字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX18封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
座面最大高度:1.46 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:13 mmBase Number Matches:1

UPD46365184BF1-E33-EQ1-A 数据手册

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Datasheet  
μPD46365084B  
μPD46365094B  
μPD46365184B  
μPD46365364B  
R10DS0090EJ0400  
Rev.4.00  
36M-BIT QDRTM II SRAM  
4-WORD BURST OPERATION  
Nov 09 2012  
Description  
The μPD46365084B is a 4,194,304-word by 8-bit, the μPD46365094B is a 4,194,304-word by 9-bit, the  
μPD46365184B is a 2,097,152-word by 18-bit and the μPD46365364B is a 1,048,576-word by 36-bit  
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-  
transistor memory cell.  
The μPD46365084B, μPD46365094B, μPD46365184B and μPD46365364B integrate unique synchronous  
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are  
latched on the positive edge of K and K#. These products are suitable for application which require  
synchronous operation, high speed, low voltage, high density and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA (13 x 15)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR READ and WRITE operation  
Four-tick burst for reduced address frequency  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.  
User programmable impedance output (35 to 70 Ω)  
Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz)  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
R10DS0090EJ0400 Rev.4.00  
Nov 09, 2012  
Page 1 of 38  

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