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UPD46184095BF1-E40-EQ1 PDF预览

UPD46184095BF1-E40-EQ1

更新时间: 2023-12-18 00:00:00
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
34页 595K
描述
DDR SRAM

UPD46184095BF1-E40-EQ1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LBGA
包装说明:BGA-165针数:165
Reach Compliance Code:unknownFactory Lead Time:1 week
风险等级:5.79最长访问时间:0.45 ns
最大时钟频率 (fCLK):250 MHzI/O 类型:SEPARATE
JESD-30 代码:R-PBGA-B165长度:15 mm
内存密度:18874368 bit内存集成电路类型:DDR SRAM
内存宽度:9功能数量:1
端子数量:165字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX9输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
电源:1.5/1.8,1.8 V认证状态:Not Qualified
座面最大高度:1.46 mm最大待机电流:0.38 A
最小待机电流:1.7 V子类别:SRAMs
最大压摆率:0.45 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:13 mmBase Number Matches:1

UPD46184095BF1-E40-EQ1 数据手册

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Datasheet  
μPD46184095B  
μPD46184185B  
R10DS0115EJ0200  
Rev.2.00  
18M-BIT DDR II SRAM SEPARATE I/O  
2-WORD BURST OPERATION  
Nov 09, 2012  
Description  
The μPD46184095B is a 2,097,152-word by 9-bit and the μPD46184185B is a 1,048,576-word by 18-bit synchronous  
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD46184095B and μPD46184185B integrate unique synchronous peripheral circuitry and a burst counter. All input  
registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density and  
wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 0.1 V power supply  
165-pin PLASTIC BGA (13 x 15)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports  
DDR read or write operation initiated each cycle  
Pipelined double data rate operation  
Separate data input/output bus  
Two-tick burst for low DDR transaction size  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time and clock skew matching-clock  
and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.  
User programmable impedance output (35 to 70 Ω)  
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
R10DS0115EJ0200 Rev.2.00  
Nov 09, 2012  
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