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UPD4516161AG5-A10B-9NF PDF预览

UPD4516161AG5-A10B-9NF

更新时间: 2024-01-02 20:39:08
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
88页 1099K
描述
Synchronous DRAM, 1MX16, 7ns, MOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50

UPD4516161AG5-A10B-9NF 技术参数

生命周期:Obsolete包装说明:0.400 INCH, PLASTIC, TSOP2-50
Reach Compliance Code:unknown风险等级:5.51
访问模式:DUAL BANK PAGE BURST最长访问时间:7 ns
JESD-30 代码:R-PDSO-G50长度:20.86 mm
内存密度:16777216 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:MOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm

UPD4516161AG5-A10B-9NF 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD4516421A, 4516821A, 4516161A for Rev.P  
16M-bit Synchronous DRAM  
2-banks, LVTTL  
Description  
The µPD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access  
memories, organized as 2,097,152 × 4 × 2, 1,048,576 × 8 × 2, 524,288 × 16 × 2 (word × bit × bank), respectively.  
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.  
All inputs and outputs are synchronized with the positive edge of the clock.  
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).  
These products are packaged in 44-pin TSOP (II) (× 4, × 8) and 50-pin TSOP (II) (× 16).  
Features  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Dual internal banks controlled by A11(Bank Select)  
Byte control (×16) by LDQM and UDQM  
Programmable Wrap sequence (Sequential / Interleave)  
Programmable burst length (1, 2, 4, 8 and full page)  
Programmable /CAS latency (2 and 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
• ×4, ×8, ×16 organization  
Single 3.3 V ± 0.3 V power supply  
LVTTL compatible inputs and outputs  
2,048 refresh cycles / 32 ms  
Burst termination by Burst stop command and Precharge command  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0122N10 (Ver.1.0)  
(Previous No. M12939EJ3V0DS00)  
Date Published May 2001 CP (K)  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  
Printed in Japan  

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