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UPD4482323GF-A60Y PDF预览

UPD4482323GF-A60Y

更新时间： 2024-01-24 18:43:43
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器
页数 文件大小 规格书
28页 298K
描述
8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT

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UPD4482323GF-A60Y 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：8388608 bit内存集成电路类型：CACHE SRAM
内存宽度：32功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX32封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

UPD4482323GF-A60Y 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD4482163, 4482183, 4482323, 4482363  
8M-BIT CMOS SYNCHRONOUS FAST SRAM  
PIPELINED OPERATION  
DOUBLE CYCLE DESELECT  
Description  
The µPD4482163 is a 524,288-word by 16-bit, the µPD4482183 is a 524,288-word by 18-bit, µPD4482323 is a 262,144-  
word by 32-bit and the µPD4482363 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS  
technology using Full-CMOS six-transistor memory cell.  
The µPD4482163, µPD4482183, µPD4482323 and µPD4482363 integrates unique synchronous peripheral circuitry, 2-  
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single  
clock input (CLK).  
The µPD4482163, µPD4482183, µPD4482323 and µPD4482363 are suitable for applications which require synchronous  
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In  
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.  
The µPD4482163, µPD4482183, µPD4482323 and µPD4482363 are packaged in 100-pin PLASTIC LQFP with a 1.4  
mm package thickness for high density and low capacitive loading.  
Features  
• Single 3.3 V power supply  
• Synchronous operation  
• Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60)  
TA = −40 to +85 °C (-A44Y, -A50Y, -A60Y)  
• Internally self-timed write control  
• Burst read / write : Interleaved burst and linear burst sequence  
• Fully registered inputs and outputs for pipelined operation  
• Double-Cycle deselect timing  
• All registers triggered off positive clock edge  
• 3.3 V LVTTL Compatible : All inputs and outputs  
• Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)  
• Asynchronous output enable : /G  
• Burst sequence selectable : MODE  
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
• Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482323, µPD4482363)  
/BW1, /BW2, /BWE (µPD4482163, µPD4482183)  
Global write enable : /GW  
• Three chip enables for easy depth expansion  
• Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M14904EJ3V0DS00 (3rd edition)  
Date Published December 2002 NS CP(K)  
Printed in Japan  
The mark  shows major revised points.  
The mark # shows major revised points.  
2000  
1234567...28

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