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UPD4442161GF-A85 PDF预览

UPD4442161GF-A85

更新时间: 2024-01-08 00:06:03
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
24页 196K
描述
Cache SRAM, 256KX16, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

UPD4442161GF-A85 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
最长访问时间:8.5 ns最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
端子数量:100字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:PARALLEL
电源:2.5/3.3,3.3 V认证状态:Not Qualified
最大待机电流:0.012 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.28 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUADBase Number Matches:1

UPD4442161GF-A85 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD4442161, 4442181, 4442321, 4442361  
4M-BIT CMOS SYNCHRONOUS FAST SRAM  
FLOW THROUGH OPERATION  
Description  
The µPD4442161 is a 262,144-word by 16-bit, the µPD4442181 is a 262,144-word by 18-bit, the µPD4442321 is a  
131,072-word by 32-bit and the µPD4442361 is a 131,072-word by 36-bit synchronous static RAM fabricated with  
advanced CMOS technology using Full-CMOS six-transistor memory cell.  
The µPD4442161, µPD4442181, µPD4442321 and µPD4442361 integrate unique synchronous peripheral circuitry,  
2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the  
single clock input (CLK).  
The µPD4442161, µPD4442181, µPD4442321 and µPD4442361 are suitable for applications which require  
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer  
memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).  
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal  
operation.  
The µPD4442161, µPD4442181, µPD4442321 and µPD4442361 are packaged in 100-pin PLASTIC LQFP with a  
1.4 mm package thickness for high density and low capacitive loading.  
Features  
3.3 V (A version) or 2.5 V (C version) Core Supply  
Synchronous operation  
Internally self-timed write control  
Burst read / write : Interleaved burst and linear burst sequence  
Fully registered inputs for flow through operation  
All registers triggered off positive clock edge  
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs  
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)  
Asynchronous output enable : /G  
Burst sequence selectable : MODE  
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
Separate byte write enable : /BW1 - /BW4 (µPD4442321, µPD4442361), /BW1 - /BW2 (µPD4442161,  
µPD4442181), /BWE  
Global write enable : /GW  
Three chip enables for easy depth expansion  
Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
The mark shows major revised points.  
Document No. M14519EJ2V0DS00 (2nd edition)  
Date Published May 2001 NS CP(K)  
Printed in Japan  
2000  
©

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