Datasheet > UPD44322361F1-A85-FQ2

UPD44322361F1-A85-FQ2

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
日电电子 - NEC		静态存储器
页数	文件大小	规格书
40页	739K
描述
Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44322181, 44322321, 44322361

32M-BIT CMOS SYNCHRONOUS FAST SRAM

FLOW THROUGH OPERATION

Description

The µPD44322181 is a 2,097,152-word by 18-bit, the µPD44322321 is a 1,048,576-word by 32-bit and the

µPD44322361 is a 1,048,576-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using

Full-CMOS six-transistor memory cell.

The µPD44322181, µPD44322321 and µPD44322361 integrate unique synchronous peripheral circuitry, 2-bit burst

counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock

input (CLK).

The µPD44322181, µPD44322321 and µPD44322361 are suitable for applications which require synchronous operation,

high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The µPD44322181, µPD44322321 and µPD44322361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package

thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.

Features

• 3.3 V or 2.5 V core supply

• Synchronous operation

• Operating temperature : T^A= 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)

T^A= –40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs for flow through operation

• All registers triggered off positive clock edge

• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4, /BWE (µPD44322321, µPD44322361)

/BW1, /BW2, /BWE (µPD44322181)

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with NEC Electronics sales

representative for availability and additional information.

The mark

shows major revised points.

Document No. M16026EJ1V0DS00 (1st edition)

Date Published December 2002 NS CP(K)

Printed in Japan

2002

12 3 4 5 6 7...40

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与UPD44322361F1-A85-FQ2相关器件

型号	品牌	描述	获取价格	数据表
UPD44322361F1-C85-FQ2	NEC	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165	获取价格
UPD44322361F1-C85Y-FQ2	NEC	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165	获取价格
UPD44322361GF-A65	NEC	Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100	获取价格
UPD44322361GF-A65Y	NEC	Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100	获取价格
UPD44322361GF-A85	NEC	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100	获取价格
UPD44322361GF-C75	NEC	Cache SRAM, 1MX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100	获取价格

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